公开(公告)号：US20140110851A1

公开(公告)日：2014-04-24

申请号：US14045648

申请日：2013-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam KIM ,  Sun-Young PARK ,  Soo-Ho SHIN ,  Kye-Hee YEOM ,  Hyeon-Woo JANG ,  Jin-Won JEONG ,  Chang-Hyun CHO ,  Hyeong-sun HONG

IPC: H01L23/48

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US20190362791A1

公开(公告)日：2019-11-28

申请号：US16533143

申请日：2019-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-woo KIM ,  Jae-kyu LEE ,  Ki-seok SUH ,  Hyeong-sun HONG ,  Yoo-sang HWANG ,  Gwan-hyeob KOH

IPC: G11C14/00 ,  H01L27/22 ,  H01L27/108 ,  H01L27/24 ,  H01L45/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L29/423 ,  H01L23/528 ,  H01L29/08 ,  H01L27/105 ,  H01L27/02 ,  G11C11/00 ,  G11C7/10

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

公开(公告)号：US20130113029A1

公开(公告)日：2013-05-09

申请号：US13724799

申请日：2012-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-woo Chung ,  Yong-chul OH ,  Yoo-sang HWANG ,  Gyo-young JIN ,  Hyeong-sun HONG ,  Dae-ik KIM

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

Abstract: A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed betweenthe first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

Abstract translation: 半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向 ，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上， 所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向 以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。