公开(公告)号：US11828791B2

公开(公告)日：2023-11-28

申请号：US17549005

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijae Song ,  Jongkook Kim ,  Dongho Lee ,  Seonmi Lee

IPC: G01R31/28 ,  G01R1/04

CPC classification number: G01R31/2863 ,  G01R1/0441 ,  G01R1/0491 ,  G01R31/2889

Abstract: A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

公开(公告)号：US09759741B2

公开(公告)日：2017-09-12

申请号：US14863703

申请日：2015-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyong Park ,  Yong chul Jang ,  Kijae Song

IPC: G01R1/04 ,  G01R31/28

CPC classification number: G01R1/0408 ,  G01R31/2889 ,  H01L2224/16225

Abstract: Provided is a test board including a main board which is configured to be connected to a plurality of devices-under-test (DUTs) and includes a plurality of test signal paths for transmitting a plurality of test signals input from an external tester to pins of at least one of the DUTs or transmitting a test result from the DUT to the tester, and a farm board which is connected to the main board and configured to mount therein a plurality of passive elements which are configured to be connected to at least one of the pins of the DUT through at least one of the test signal paths of the main board, when a test operation is performed, thereby improving a power integrity property or a signal integrity property in the test operation.

公开(公告)号：US20150058685A1

公开(公告)日：2015-02-26

申请号：US14293983

申请日：2014-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： UNGJIN JANG ,  Kijae Song ,  Sang Kyeong Han

IPC: G11C29/10

CPC classification number: G11C29/16 ,  G11C2029/0401

Abstract: A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a DUT under the control of a DQ signal responding to a DQ enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array. The programmed logical value is captured from the DUT under the control the DQ signal. The generated logical value is compared with the captured logical value. Whether the DUT is defective is determined according to a result of the comparison. The DQ enable signal is applied to a time point different from a time point when a SYNC clock for synchronizing the automatic test equipment with the field programmable gate array is applied.

Abstract translation: 测试半导体存储器的方法包括通过包括在现场可编程门阵列中的算法模式发生器产生测试模式的逻辑值。 所产生的逻辑值在DUT中被控制，在DQ信号的控制下响应于从自动测试设备产生的DQ使能信号，然后传送到现场可编程门阵列。 在DQ信号的控制下，从DUT捕获编程逻辑值。 将生成的逻辑值与捕获的逻辑值进行比较。 根据比较的结果确定DUT是否有缺陷。 DQ使能信号被施加到与用于使自动测试设备与现场可编程门阵列同步的SYNC时钟不同的时间点。