公开(公告)号：US20200006188A1

公开(公告)日：2020-01-02

申请号：US16566380

申请日：2019-09-10

申请人： Samsung Electronics Co., Ltd.

发明人： Min-Ok Na ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC分类号： H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065

摘要： Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

公开(公告)号：US10211159B2

公开(公告)日：2019-02-19

申请号：US15215227

申请日：2016-07-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31 ,  H01L23/498

摘要： A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US09252031B2

公开(公告)日：2016-02-02

申请号：US14493379

申请日：2014-09-23

申请人： Samsung Electronics Co., Ltd.

发明人： Hohyeuk Im ,  Jongkook Kim ,  Gowoon Seong ,  SeokWon Lee ,  Byoungwook Jang ,  Eunseok Cho

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05599

摘要： Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.

摘要翻译： 提供了一种半导体封装，其包括下封装，下封装上的插入件和插入件上的上封装。 下封装可以包括下封装衬底，下封装衬底上的下半导体芯片和下半导体芯片上的下传热层。 插入器可以包括插入器基板，分别由插入器基板的凹入的底部和顶部表面限定的第一和第二传热开口，设置在第二传热开口中的上插入件传热垫，以及上部热 - 转移层，设置在上部插入件传热垫上。 上封装可以包括上封装衬底，上封装传热垫，其可以设置在由上封装衬底的凹陷底表面限定的第三传热开口中，以及设置在上封装衬底上的上半导体芯片 封装衬底。

公开(公告)号：US20240274579A1

公开(公告)日：2024-08-15

申请号：US18417264

申请日：2024-01-19

申请人： Samsung Electronics Co., Ltd.

发明人： Choongbin Yim ,  Jongkook Kim

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H10B80/00

CPC分类号： H01L25/0657 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225

摘要： A semiconductor package includes a chip structure including a first stack semiconductor chip, which includes a first sub-chip and a second sub-chip that is bonded to the first sub-chip and is of a different type from the first sub-chip, a first molding layer configured to mold the second sub-chip on the first sub-chip, and a first redistribution structure arranged above the first stack semiconductor chip and the first molding layer, a second redistribution structure arranged under the chip structure and bonded to the chip structure, a bonding wire electrically connecting the second redistribution structure to the first redistribution structure, and a second molding layer configured to seal, on the second redistribution structure, the chip structure and the bonding wire.

公开(公告)号：US11828791B2

公开(公告)日：2023-11-28

申请号：US17549005

申请日：2021-12-13

申请人： Samsung Electronics Co., Ltd.

发明人： Kijae Song ,  Jongkook Kim ,  Dongho Lee ,  Seonmi Lee

IPC分类号： G01R31/28 ,  G01R1/04

CPC分类号： G01R31/2863 ,  G01R1/0441 ,  G01R1/0491 ,  G01R31/2889

摘要： A test board for testing a semiconductor apparatus includes a first board configured to support a plurality of first Devices Under Test (DUTs) such that the plurality of first DUTs are mounted on the first board, a plurality of first inter-board connectors arranged on the first board, and a plurality of second boards stacked on the first board through the plurality of first inter-board connectors, each second board of the plurality of second boards having a surface configured to support a separate second DUT of a plurality of second DUTs such that the plurality of second DUTs are mounted on separate, respective second boards of the plurality of second board.

公开(公告)号：US20240355802A1

公开(公告)日：2024-10-24

申请号：US18384912

申请日：2023-10-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Chengtar WU ,  Jongkook Kim

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

CPC分类号： H01L25/18 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L28/60 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204

摘要： A three-dimensional integrated circuit structure includes: a first semiconductor die; and a second semiconductor die disposed on the first semiconductor die, wherein the first semiconductor die includes: a plurality of through-silicon vias (TSV); and a plurality of integrated stack capacitor (ISC) chips, wherein each of the plurality of ISC chips is disposed between adjacent through-silicon vias among the plurality of through-silicon vias.

公开(公告)号：US10825776B2

公开(公告)日：2020-11-03

申请号：US16240174

申请日：2019-01-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yoonha Jung ,  Jongkook Kim ,  Bona Baek ,  Heeseok Lee ,  Kyoungsei Choi

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L23/552 ,  H01L23/31

摘要： A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US10431522B2

公开(公告)日：2019-10-01

申请号：US15856800

申请日：2017-12-28

申请人： Samsung Electronics Co., Ltd.

发明人： Min-Ok Na ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC分类号： H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

摘要： Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

公开(公告)号：US20240355794A1

公开(公告)日：2024-10-24

申请号：US18497039

申请日：2023-10-30

申请人： Samsung Electronics Co., Ltd.

发明人： Choongbin Yim ,  Jongkook Kim ,  Chengtar Wu

IPC分类号： H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H10B80/00

CPC分类号： H01L25/105 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/3511

摘要： A semiconductor package may include: a redistribution layer structure; a semiconductor structure on the redistribution layer structure; a printed circuit board on the redistribution layer structure and extending around a side surface of the semiconductor structure; a molding material extending around the semiconductor structure on the redistribution layer structure; and a silicon interposer on the printed circuit board and the molding material.

公开(公告)号：US10950521B2

公开(公告)日：2021-03-16

申请号：US16566380

申请日：2019-09-10

申请人： Samsung Electronics Co., Ltd.

发明人： Min-Ok Na ,  Jongkook Kim ,  Hyo-Chang Ryu ,  Jin-woo Park ,  BongJin Son ,  Jangwoo Lee

IPC分类号： H01L23/373 ,  H01L23/367 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

摘要： Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.