METHOD FOR OPERATING A NON VOLATILE MEMORY OF AN ELECTRONIC DEVICE AND THE ELECTRONIC DEVICE IMPLEMENTING THE SAME
    2.
    发明申请
    METHOD FOR OPERATING A NON VOLATILE MEMORY OF AN ELECTRONIC DEVICE AND THE ELECTRONIC DEVICE IMPLEMENTING THE SAME 审中-公开
    用于操作电子设备的非易失性存储器的方法和实现该电子设备的电子设备

    公开(公告)号:US20160335011A1

    公开(公告)日:2016-11-17

    申请号:US15153633

    申请日:2016-05-12

    Abstract: Various embodiments of the present disclosure provide a method of operating a non-volatile memory and an electronic device adapted to the method. When the possibility that power will be cut off in the electronic device is low or almost zero, the provision operation (e.g., an LSB backup) is interrupted which is capable of preventing data from being erased against a situation where the power is cut off. The method of managing a storage device includes: transferring an initialization command to a non-volatile memory functionally connected to a storage device; transferring a command for interrupting or executing an LSB backup to the storage device controller included in the non-volatile memory; and interrupting or executing, by the storage device controller, the LSB backup according to the LSB backup interrupt or execute command. Other modifications are provided.

    Abstract translation: 本公开的各种实施例提供了一种操作非易失性存储器的方法和适用于该方法的电子设备。 当电子设备中的电力被切断的可能性低或几乎为零时,中断提供操作(例如,LSB备份),其能够防止在电力被切断的情况下数据被擦除。 管理存储设备的方法包括:将初始化命令传送到功能上连接到存储设备的非易失性存储器; 将用于中断或执行LSB备份的命令传送到包括在非易失性存储器中的存储设备控制器; 并且由存储设备控制器根据LSB备份中断或执行命令中断或执行LSB备份。 提供其他修改。

    Three-dimensional semiconductor memory device and method for fabricating the same
    3.
    发明授权
    Three-dimensional semiconductor memory device and method for fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号:US09076879B2

    公开(公告)日:2015-07-07

    申请号:US13974122

    申请日:2013-08-23

    Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.

    Abstract translation: 一种三维(3D)半导体存储器件及其制造方法,该器件包括堆叠在衬底上的绝缘层; 绝缘层之间的水平结构,分别包括栅电极的水平结构; 垂直结构分别穿透绝缘层和水平结构,垂直结构分别包括半导体柱; 和外延图案,每个外延图案在衬底和每个垂直结构之间,其中外延图案的最小宽度小于垂直结构中对应的一个的宽度。

    Memory system storage device including path circuit in parallel with auxiliary power device

    公开(公告)号:US11295785B2

    公开(公告)日:2022-04-05

    申请号:US16877752

    申请日:2020-05-19

    Abstract: A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

    Electronic device including antenna feeding unit

    公开(公告)号:US12095176B2

    公开(公告)日:2024-09-17

    申请号:US17682615

    申请日:2022-02-28

    CPC classification number: H01Q5/335 H01Q1/243

    Abstract: An electronic device is provided. The electronic device includes an antenna, a wireless communication module electrically connected to the antenna, a flexible printed circuit board (FPCB) including a first feeding element and a second feeding element which are electrically connected to the wireless communication module, a substrate disposed above the first feeding element and the second feeding element, a first conductive pattern including a first coupling hole and a second conductive pattern including a second coupling hole, which are formed on the upper surface of the substrate, a first coupling fastener configured to penetrate the first coupling hole and the first feeding element and electrically connect the first conductive pattern and the first feeding element, and a second coupling fastener configured to penetrate the second coupling hole and the second feeding element and electrically connect the second conductive pattern and the second feeding element.

    Memory system storage device with power loss protection circuit

    公开(公告)号:US11854645B2

    公开(公告)日:2023-12-26

    申请号:US17694946

    申请日:2022-03-15

    CPC classification number: G11C5/005 G11C5/141

    Abstract: A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

Patent Agency Ranking