公开(公告)号：US20200350312A1

公开(公告)日：2020-11-05

申请号：US16935487

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Heon-jong Shin ,  In-chan Hwang ,  Jae-ran Jang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/265 ,  H01L27/02 ,  H01L21/762 ,  H01L21/761 ,  H01L23/528 ,  H01L29/78

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

公开(公告)号：US12249648B2

公开(公告)日：2025-03-11

申请号：US17857608

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Seung Song ,  Hyo-Jin Kim ,  Kyoung-Mi Park ,  Hwi-Chan Jun ,  Seung-Seok Ha

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

公开(公告)号：US11616016B2

公开(公告)日：2023-03-28

申请号：US17235425

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Seul-Ki Hong ,  Hyun-Soo Kim ,  Sang-Hyun Lee

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

公开(公告)号：US09640529B2

公开(公告)日：2017-05-02

申请号：US15196781

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hwi-Chan Jun

IPC: H01L27/06 ,  H01L21/285 ,  H01L49/02 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/51

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53266 ,  H01L23/535 ,  H01L28/24 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

公开(公告)号：US20210242126A1

公开(公告)日：2021-08-05

申请号：US17235425

申请日：2021-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Seul-Ki Hong ,  Hyun-Soo Kim ,  Sang-Hyun Lee

IPC: H01L23/528 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

公开(公告)号：US10177093B2

公开(公告)日：2019-01-08

申请号：US15497283

申请日：2017-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US09876094B2

公开(公告)日：2018-01-23

申请号：US14984037

申请日：2015-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok-Han Bae ,  Kyung-Soo Kim ,  Chul-Sung Kim ,  Woo-Cheol Shin ,  Hwi-Chan Jun

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.

公开(公告)号：US20160020148A1

公开(公告)日：2016-01-21

申请号：US14668430

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hwi-Chan Jun

IPC: H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/45 ,  H01L21/285 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53266 ,  H01L23/535 ,  H01L28/24 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

公开(公告)号：US11935835B2

公开(公告)日：2024-03-19

申请号：US17120616

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chul-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/76831 ,  H01L21/76889 ,  H01L21/823481

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US11769769B2

公开(公告)日：2023-09-26

申请号：US17699609

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Heon-jong Shin ,  In-chan Hwang ,  Jae-ran Jang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/265 ,  H01L27/02 ,  H01L21/762 ,  H01L21/761 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7854

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.