中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.035 seconds)

    Semiconductor device and method of fabricating the same
    1.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US11355434B2

    公开(公告)日：2022-06-07

    申请号：US17016977

    申请日：2020-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Seung Song ,  Kwang-Young Lee ,  Jonghyun Lee

    IPC: H01L23/528 ,  H01L27/11 ,  H01L21/768 ,  H01L29/78

    Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

    Semiconductor devices
    3.
    发明授权
    Semiconductor devices 有权
    半导体器件

    公开(公告)号：US09406663B2

    公开(公告)日：2016-08-02

    申请号：US14161867

    申请日：2014-01-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Seung Song ,  Kyung-Eun Kim ,  Jae-Kyun Park

    IPC: H01L27/02 ,  H01L27/11 ,  H01L27/118

    CPC classification number: H01L27/0207 ,  H01L27/1104 ,  H01L2027/11812 ,  H01L2027/11838

    Abstract: Semiconductor devices include a first gate pattern provided on the first active region, a second gate pattern over the first active region, a third gate pattern over the second active region, and a fourth gate pattern over the second active region. The second gate pattern is parallel to the first gate pattern in a first direction. The third gate pattern has an asymmetric shape to the first gate pattern with respect to the first direction, and the fourth gate pattern is parallel to the third gate pattern in the first direction, and has an asymmetric shape to the second gate pattern with respect to the first direction. MOS transistors having good properties may be provided in a narrow horizontal area. The MOS transistors may be used in highly stacked semiconductor devices.

    Abstract translation: 半导体器件包括设置在第一有源区上的第一栅极图案，第一有源区上的第二栅极图案，第二有源区上的第三栅极图案，以及第二有源区上的第四栅极图案。 第二栅极图案在第一方向上平行于第一栅极图案。 第三栅极图案相对于第一方向具有与第一栅极图案不对称的形状，并且第四栅极图案在第一方向上平行于第三栅极图案，并且相对于第二栅极图案具有与第二栅极图案不对称的形状 第一个方向。 可以在窄的水平区域中提供具有良好性能的MOS晶体管。 MOS晶体管可以用于高度堆叠的半导体器件中。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240297232A1

    公开(公告)日：2024-09-05

    申请号：US18655409

    申请日：2024-05-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Seung Song ,  Tae-Yeol Kim ,  Jae-Jik Baek

    IPC: H01L29/417 ,  H01L23/522 ,  H01L29/40

    CPC classification number: H01L29/41775 ,  H01L23/5226 ,  H01L29/401

    Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

    Method of fabricating semiconductor device
    5.
    发明授权
    Method of fabricating semiconductor device 有权

    公开(公告)号：US11923298B2

    公开(公告)日：2024-03-05

    申请号：US17830811

    申请日：2022-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Seung Song ,  Kwang-Young Lee ,  Jonghyun Lee

    IPC: H01L23/528 ,  H01L21/768 ,  H10B10/00 ,  H01L29/78

    CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76834 ,  H10B10/12 ,  H01L21/76843 ,  H01L29/785

    Abstract: A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220199798A1

    公开(公告)日：2022-06-23

    申请号：US17457661

    申请日：2021-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myung Gil Kang ,  Keun Hwi Cho ,  Sangdeok Kwon ,  Dongwon Kim ,  Hyun-Seung Song

    IPC: H01L29/423 ,  H01L23/522 ,  H01L27/088 ,  H01L29/786

    Abstract: A semiconductor device includes a substrate that includes a peripheral region, a first active pattern on the peripheral region, a first source/drain pattern on the first active pattern, a first channel pattern formed on the first active pattern and connected to the first source/drain pattern, wherein the first channel pattern includes semiconductor patterns that are stacked and spaced apart from each other, a first gate electrode that extends in a first direction and crosses the first channel pattern, a gate insulating layer interposed between the first gate electrode and the first channel pattern, a first gate contact disposed on the first gate electrode and that extends in the first direction, and a first dielectric layer interposed between the first gate electrode and the first gate contact. The first dielectric layer is interposed between the first gate contact and the first gate electrode and extends in the first direction.

    Methods of Fabricating Semiconductor Devices Having Punch-Through Stopping Regions
    9.
    发明申请
    Methods of Fabricating Semiconductor Devices Having Punch-Through Stopping Regions 有权
    制造具有穿通停止区域的半导体器件的方法

    公开(公告)号：US20150044829A1

    公开(公告)日：2015-02-12

    申请号：US14454943

    申请日：2014-08-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Un Kim ,  Hyun-Seung Song ,  Dong-Hyun Kim

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/266

    CPC classification number: H01L29/7851 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/66803

    Abstract: Methods of fabricating semiconductor devices are provided including providing a substrate having a first region and a second region, the substrate defining trenches in the first and second regions; forming active fins on the first and second regions, the active fins protruding from the trenches in the first and second regions; forming spacers on sidewalls of the active fins in the first and second regions; recessing floors of the trenches under the spacers to provide extensions of the active fins; implanting impurities of a first type in the extensions of the active fins in the first region; and implanting impurities of a second, type, different from the first type, in the extensions of the active fins in the second region.

    Abstract translation: 提供制造半导体器件的方法包括提供具有第一区域和第二区域的衬底，所述衬底限定第一和第二区域中的沟槽; 在所述第一和第二区域上形成活动翅片，所述活动翅片从所述第一和第二区域中的沟槽突出; 在所述第一和第二区域中的活动翅片的侧壁上形成间隔物; 在间隔物下方的沟槽的凹陷地板，以提供活动鳍片的延伸; 将第一类型的杂质植入第一区域中活性鳍片的延伸部分; 以及将第二类型的不同于第一类型的杂质植入第二区域中的活性鳍片的延伸部分。

Patent Agency Ranking