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公开(公告)号：US20140376310A1
公开(公告)日：2014-12-25
申请号：US14272906
申请日：2014-05-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Si-Hwan KIM , Sang-Yong YOON , Kyung-Ryun KIM
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/3459
Abstract: A method of writing data in a non-volatile memory device includes receiving a program command and a first row address corresponding to a first word line; performing a first partial programming operation with respect to first memory cells coupled to the first word line; performing a second partial programming operation with respect to second memory cells coupled to a second word line adjacent to the first word line; performing a first verification operation by verifying the first partial programming operation; and selectively performing a first additional programming operation with respect to the first memory cells depending on a result of the first verification operation.
Abstract translation: 一种在非易失性存储器件中写入数据的方法包括：接收与第一字线对应的程序命令和第一行地址; 对与第一字线耦合的第一存储器单元执行第一部分编程操作; 对与第一字线相邻的第二字线耦合的第二存储器单元执行第二部分编程操作; 通过验证第一部分编程操作来执行第一验证操作; 以及根据所述第一验证操作的结果选择性地执行关于所述第一存储器单元的第一附加编程操作。
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Patent Agency Ranking
2.发明申请公开(公告)号：US20190304565A1
公开(公告)日：2019-10-03
申请号：US16283650
申请日：2019-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Ryun KIM , Yoon-Na OH , Hyung-Jin KIM , Hui-Kap YANG , Jang-Woo RYU
Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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3.发明申请公开(公告)号：US20190096508A1
公开(公告)日：2019-03-28
申请号：US16023584
申请日：2018-06-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyung-Ryun KIM , Hyun-Chul YOON
IPC: G11C29/00 , G11C11/408 , G11C11/4076 , G11C11/4091 , G11C11/4094
Abstract: A semiconductor memory device may include a memory cell array and an access control circuit. The memory cell array may include a first cell region and a second cell region. The access control circuit may access the first cell region and the second cell region differently in response to a command, an access address and fuse information to identify the first cell region and the second cell region. The command and the address may be provided from an external device.
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4.发明申请公开(公告)号：US20220238178A1
公开(公告)日：2022-07-28
申请号：US17723200
申请日：2022-04-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Ryun KIM , Yoon-Na OH , Hyung-Jin KIM , Hui-Kap YANG , Jang-Woo RYU
Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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5.发明申请公开(公告)号：US20210233604A1
公开(公告)日：2021-07-29
申请号：US17216160
申请日：2021-03-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Ryun KIM , Yoon-Na OH , Hyung-Jin KIM , Hui-Kap YANG , Jang-Woo RYU
Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
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公开(公告)号：US20190164621A1
公开(公告)日：2019-05-30
申请号：US16130544
申请日：2018-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Ryun KIM
Abstract: A semiconductor memory device a memory cell array and a repair control circuit. The memory cell array including a normal cell region and a redundancy cell region, the normal cell region including a plurality of normal region groups, and redundancy cell region configured to replace failed memory cells of the normal cell region. The repair control circuit configured to, determine a target normal region group from among the plurality of normal region groups based on an input address, extract target fail addresses from among a plurality of fail addresses based on the target normal region group, and control a repair operation based on the target fail addresses and the input address.
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