公开(公告)号：US20240170552A1

公开(公告)日：2024-05-23

申请号：US18215254

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungbin Chun ,  Jinbum Kim ,  Gyeom Kim ,  Dahye Kim ,  Youngkwang Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including channels spaced apart from each other on a substrate; a gate structure extending on the substrate, the gate structure surrounding lower and upper surfaces and sidewalls of each of the channels; and a source/drain layer on the substrate, the source/drain layer contacting sidewalls of the channels and containing silicon-germanium, the source/drain layer including: a second epitaxial layer having a second germanium concentration; and a first epitaxial layer having a first germanium concentration smaller than the second germanium concentration, the first epitaxial layer covering a lower surface and sidewalls of the second epitaxial layer, wherein the first epitaxial layer includes a protruding portion that protrudes in the first direction and contacts the gate structure, and wherein the protruding portion has a facet that is not curved.

公开(公告)号：US20230317792A1

公开(公告)日：2023-10-05

申请号：US18073806

申请日：2022-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Dahye Kim ,  Kyungbin Chun

IPC: H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes an active region, a plurality of channel layers disposed to be spaced apart from each other in a vertical direction on the active region, a gate structure extending in a second direction to intersect the active region and the plurality of channel layers and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers, and a contact plug connected to the source/drain region. The source/drain region includes a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers, second epitaxial layers disposed on the first epitaxial layer, each including impurities in a first concentration, and doping layers stacked alternately with the second epitaxial layers, each including the impurities in a second concentration higher than the first concentration.