公开(公告)号：US12019861B2

公开(公告)日：2024-06-25

申请号：US17051588

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhwa Oh ,  Woochan Kim ,  Dahye Kim ,  Sookkyung Lee ,  Hyunbin Lee ,  Dale Ahn ,  Seunghwan Hong

IPC: G06F3/04883 ,  G06F3/04842 ,  G06F40/171 ,  G06V30/32

CPC classification number: G06F3/04883 ,  G06F3/04842 ,  G06F40/171 ,  G06V30/32

Abstract: An electronic device is provided. The electronic device includes a display, a sensing panel, and a processor operatively connected with the display and the sensing panel, wherein the processor is configured to display content on the display, display an object corresponding to a handwriting input on the content, based on the handwriting input sensed by the sensing panel, in response to a first keyword being recognized based on at least part of the handwriting input, perform character recognition on an additional handwriting input entered after input of the first keyword, and in response to a character recognition end event being identified, provide text obtained by the character recognition on the additional handwriting input as a hashtag for the displayed content.

公开(公告)号：US11942586B2

公开(公告)日：2024-03-26

申请号：US17693704

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

IPC: H01L33/62 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H01L25/075 ,  H01L25/16 ,  H01L27/15 ,  H01L33/48 ,  H01L33/56 ,  H01L25/00

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L33/56

Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.

公开(公告)号：US11664453B2

公开(公告)日：2023-05-30

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Dahye Kim ,  Jinbum Kim ,  Gyeom Kim ,  Dohee Kim ,  Dongwoo Kim ,  Seunghun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/04

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US11626401B2

公开(公告)日：2023-04-11

申请号：US16991530

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Dahye Kim ,  Jinbum Kim ,  Kyungin Choi ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

公开(公告)号：US11094832B2

公开(公告)日：2021-08-17

申请号：US16744642

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye Kim ,  Dongchan Suh ,  Jinbum Kim

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.

公开(公告)号：US20210066560A1

公开(公告)日：2021-03-04

申请号：US16860255

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dahye Kim ,  Seokhyun Lee ,  Jungho Park

IPC: H01L33/62 ,  H01L33/56 ,  H01L33/48

Abstract: A display module package includes a semiconductor chip, a wiring member disposed on the semiconductor chip, including an insulating layer and a wiring layer, and contacting at least a portion of the semiconductor chip, a light emitting device array disposed on the wiring member and including a plurality of light emitting devices disposed on one surface, wherein the wiring member is between the semiconductor chip and the light emitting device, and a molding member disposed on the wiring member, sealing part of the light emitting device array, and having an opening for exposing the plurality of light emitting devices.

公开(公告)号：US12256564B2

公开(公告)日：2025-03-18

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H10D62/13 ,  H10D30/60 ,  H10D30/67 ,  H10D30/69 ,  H10D62/822 ,  H10D64/01 ,  H10D64/23 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US12046682B2

公开(公告)日：2024-07-23

申请号：US17689322

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ingyu Jang ,  Jinbum Kim ,  Dahye Kim ,  Sujin Jung ,  Dongsuk Shin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

公开(公告)号：US20230395684A1

公开(公告)日：2023-12-07

申请号：US18130070

申请日：2023-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Jinbum Kim ,  Dahye Kim ,  Ingyu Jang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region extending in a first direction on a substrate, a plurality of channel layers spaced apart from each other in a vertical direction, a gate structure enclosing the plurality of channel layers, respectively, and a source/drain region contacting the plurality of channel layers. The source/drain region includes a first epitaxial layer extending to contact the plurality of channel layers, and a second epitaxial layer on the first epitaxial layer. A surface in which the first epitaxial layer and the second epitaxial layer contact each other includes: first surfaces having a first slope; second surfaces having a second slope, different from the first slope; first bent portions between the first surfaces and the second surfaces; and a second bent portion in which the second surfaces meet.

公开(公告)号：US11791400B2

公开(公告)日：2023-10-17

申请号：US17643935

申请日：2021-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Seung Hun Lee ,  Dahye Kim ,  Ilgyou Shin ,  Sangmoon Lee ,  Kyungin Choi

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.