公开(公告)号：US20240297215A1

公开(公告)日：2024-09-05

申请号：US18658794

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0245 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US20240266256A1

公开(公告)日：2024-08-08

申请号：US18369527

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Jinbum Kim

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure provides semiconductor devices including a field effect transistor (FET) and methods of fabricating the same. In some embodiments, a semiconductor device includes a substrate, a lower power line buried in a lower portion of the substrate, a source/drain pattern on the substrate, and a backside contact that penetrates the substrate and electrically couples the lower power line to the source/drain pattern. The backside contact includes an epitaxial pattern coupled to a lower portion of the source/drain pattern, a contact plug coupled to the lower power line, and a metal-semiconductor compound layer between the epitaxial pattern and the contact plug. The epitaxial pattern includes a top surface that protrudes toward the source/drain pattern.

公开(公告)号：US11990549B2

公开(公告)日：2024-05-21

申请号：US17716005

申请日：2022-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jung ,  Jinbum Kim ,  Dongil Bae

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.

公开(公告)号：US20240162293A1

公开(公告)日：2024-05-16

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  DAHYE KIM ,  SEOKHOON KIM ,  JAEMUN KIM ,  Ilgyou Shin ,  Haejun YU ,  KYUNGIN CHOI ,  KIHYUN HWANG ,  SANGMOON LEE ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20240145542A1

公开(公告)日：2024-05-02

申请号：US18325412

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jang Ingyu ,  Jinbum Kim ,  Sujin Jung ,  Gyeom Kim ,  Dahye Kim

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern disposed on a substrate; a gate structure disposed on the active pattern; channels disposed on the substrate and that are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; a first epitaxial layer disposed on a portion of the active pattern adjacent to the gate structure; and a contact plug disposed on the first epitaxial layer. The contact plug includes a lower portion; a middle portion disposed on the lower portion, where the middle portion has a width that increases from a bottom to a top thereof along the vertical direction; and an upper portion disposed on the middle portion.

公开(公告)号：US11881510B2

公开(公告)日：2024-01-23

申请号：US17935561

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Seokhoon Kim ,  Kwanheum Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.

公开(公告)号：US11844207B2

公开(公告)日：2023-12-12

申请号：US17579919

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Youngjun Kim ,  Jinbum Kim

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/37 ,  H10B12/482

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US20230275092A1

公开(公告)日：2023-08-31

申请号：US18143767

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Jinbum Kim ,  Haejun Yu ,  Seung Hun Lee

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

公开(公告)号：US20230215866A1

公开(公告)日：2023-07-06

申请号：US18120547

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Dahye Kim ,  Jinbum Kim ,  Kyungin Choi ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/0245 ,  H01L21/823481 ,  H01L21/823475

Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

公开(公告)号：US20230059169A1

公开(公告)日：2023-02-23

申请号：US17718795

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dongmyoung Kim ,  Cheol Kim ,  Dongsuk Shin ,  Woogwan Shim ,  Seung Hun Lee ,  Soonwook Jung

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device includes: an active pattern disposed on a substrate; a source/drain pattern disposed on the active pattern; a channel pattern connected to the source/drain pattern, wherein the channel pattern includes semiconductor patterns stacked on each other and spaced apart from each other; and a gate electrode disposed on the channel pattern and extending in a first direction, wherein the gate electrode includes: a channel neighboring part adjacent to a first sidewall of a first semiconductor pattern of the stacked semiconductor patterns; and a body part spaced apart from the first semiconductor pattern, wherein the channel neighboring part is disposed between the body part and the first semiconductor pattern, wherein the first sidewall of the first semiconductor pattern has a first width, wherein the channel neighboring part has a second width less than the first width. The body part has a third width greater than the second width.