公开(公告)号：US20200152801A1

公开(公告)日：2020-05-14

申请号：US16390859

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Stephen Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.

公开(公告)号：US10825723B2

公开(公告)日：2020-11-03

申请号：US16283341

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Harsono Simka ,  Mark Stephen Rodder

IPC: H01L23/49 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

公开(公告)号：US10930768B2

公开(公告)日：2021-02-23

申请号：US16282048

申请日：2019-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna J. Obradovic ,  Kang-ill Seo ,  Mark Stephen Rodder

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least a portion of the gate spacers to expose the extension portions of the fin, and thinning the extension portions of the fin. Following the thinning of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width less than the first width.

公开(公告)号：US20200135549A1

公开(公告)日：2020-04-30

申请号：US16283341

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Harsono Simka ,  Mark Stephen Rodder

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

公开(公告)号：US09685564B2

公开(公告)日：2017-06-20

申请号：US15149722

申请日：2016-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Stephen Rodder ,  Joon Goo Hong ,  Titash Rakshit

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.

公开(公告)号：US10957786B2

公开(公告)日：2021-03-23

申请号：US16282105

申请日：2019-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna J. Obradovic ,  Mark Stephen Rodder

IPC: H01L21/70 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/324 ,  H01L21/223 ,  H01L21/225 ,  H01L29/78 ,  H01L29/10 ,  H01L29/167

Abstract: A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least portions of the gate spacers to expose the extension portions of the fin, and hydrogen annealing the extension portions of the fin. Following the hydrogen annealing of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width greater than the first width.