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1.发明授权公开(公告)号：US11475933B2
公开(公告)日：2022-10-18
申请号：US16847741
申请日：2020-04-14
发明人： Ryan Hatcher , Titash Rakshit , Jorge Kittl , Joon Goo Hong , Dharmendar Palle
摘要： A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values.
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公开(公告)号：US20210124588A1
公开(公告)日：2021-04-29
申请号：US16838971
申请日：2020-04-02
发明人： Titash Rakshit , Malik Aqeel Anwar , Ryan Hatcher
摘要： A method of pipelining inference of a neural network, which includes an i-th layer (i being an integer greater than zero), an (i+1)-th layer, and an (i+2)-th layer, includes processing a first set of i-th values of the i-th layer to generate (i+1)-th values for the (i+1)-th layer, determining a quantity of the (i+1)-th values as being sufficient for processing, and in response to the determining, processing the (i+1)-th values to generate an output value for the (i+2)-th layer while concurrently processing a second set of i-th values of the i-th layer.
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3.发明授权公开(公告)号：US10832774B2
公开(公告)日：2020-11-10
申请号：US16448820
申请日：2019-06-21
发明人： Ryan M. Hatcher , Titash Rakshit , Jorge Kittl , Rwik Sengupta , Dharmendar Palle , Joon Goo Hong
摘要： A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.
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公开(公告)号：US20200152801A1
公开(公告)日：2020-05-14
申请号：US16390859
申请日：2019-04-22
IPC分类号： H01L29/786 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L21/02 , H01L21/306 , H01L21/308 , H01L21/8238 , H01L29/66
摘要： A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.
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公开(公告)号：US10585254B2
公开(公告)日：2020-03-10
申请号：US15965154
申请日：2018-04-27
摘要： A method for providing a vertical optical via for a semiconductor substrate is described. The semiconductor substrate has a front surface and a back side. A hard mask having an aperture therein is formed on the front surface. Part of the semiconductor substrate exposed by the aperture is removed to form a via hole. The via hole has a width not exceeding one hundred micrometers and a bottom. Cladding layer(s) and core layer(s) are provided in the via hole. The core layer(s) have at least a second index of refraction greater than that of the core layer(s). A portion of the semiconductor substrate including the back side is removed to expose a bottom portion of the core layer(s) and a bottom surface of the semiconductor substrate. The vertical optical via includes the cladding and core layers. The vertical optical via extends from the front surface to the bottom surface.
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公开(公告)号：US10461751B2
公开(公告)日：2019-10-29
申请号：US16137227
申请日：2018-09-20
IPC分类号： H01L27/115 , H03K19/0944 , H01L29/51 , G06N3/063 , H03K19/20 , H01L27/118
摘要： A computing cell and method for performing a digital XNOR of an input signal and weights are described. The computing cell includes at least one pair of FE-FETs and a plurality of selection transistors. The pair(s) of FE-FETs are coupled with a plurality of input lines and store the weight. Each pair of FE-FETs includes a first FE-FET that receives the input signal and stores a first weight and a second FE-FET that receives the input signal complement and stores a second weight. The selection transistors are coupled with the pair of FE-FETs.
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公开(公告)号：US10424581B2
公开(公告)日：2019-09-24
申请号：US15276768
申请日：2016-09-26
发明人： Titash Rakshit , Mark Rodder , Rwik Sengupta
IPC分类号： H01L27/092 , H01L29/66 , H01L21/8238 , H01L29/167 , H01L23/522 , H01L23/528 , H01L29/739 , H01L29/08 , H01L29/165 , H01L27/06
摘要： An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and a tunnel field-effect transistor (TFET) between the circuit block and ground for power gating the circuit block.
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公开(公告)号：US20180300618A1
公开(公告)日：2018-10-18
申请号：US15678050
申请日：2017-08-15
IPC分类号： G06N3/063 , H01L27/112 , G06N3/04
摘要： A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.
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公开(公告)号：US10026751B2
公开(公告)日：2018-07-17
申请号：US15210867
申请日：2016-07-14
发明人： Titash Rakshit , Borna J. Obradovic , Rwik Sengupta , Wei-E Wang , Ryan Hatcher , Mark S. Rodder
IPC分类号： H01L27/01 , H01L27/12 , H01L23/522 , H01L23/528 , H01L29/24 , H01L29/45 , H01L29/78 , H01L29/423 , H01L29/66 , H01L21/84 , H01L29/10
摘要： A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include one or more transition metal dichalcogenide materials such as MoS2, WS2, WSe2, and/or combinations thereof.
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10.发明申请公开(公告)号：US20180130785A1
公开(公告)日：2018-05-10
申请号：US15442592
申请日：2017-02-24
发明人： Wei-E Wang , Titash Rakshit , Borna J. Obradovic , Chris Bowen , Mark S. Rodder
IPC分类号： H01L27/02 , H01L23/528 , H01L29/04 , H01L29/16 , H01L23/532 , H01L29/47 , H01L23/522 , H01L21/02 , H01L21/28 , H01L21/84 , H01L21/8238 , H01L21/768 , H01L21/311 , H01L27/12 , H01L27/092 , H01L29/66 , H01L27/06
CPC分类号： H01L27/0207 , H01L21/02068 , H01L21/02164 , H01L21/02175 , H01L21/02236 , H01L21/02244 , H01L21/02532 , H01L21/02595 , H01L21/28088 , H01L21/31111 , H01L21/76802 , H01L21/76877 , H01L21/8221 , H01L21/823807 , H01L21/823828 , H01L21/823842 , H01L21/823871 , H01L21/84 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L27/0688 , H01L27/092 , H01L27/1203 , H01L29/04 , H01L29/16 , H01L29/47 , H01L29/665
摘要： A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.
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