公开(公告)号：US12254621B2

公开(公告)日：2025-03-18

申请号：US17856130

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-Nyun Kim ,  Min-Cheol Kang ,  Kihyun Kim ,  Jaehoon Kim ,  Jaekyung Lim

IPC: G06K9/00 ,  G01N21/95 ,  G06T7/00 ,  H01L21/66

Abstract: Disclosed is an operating method of an electronic device for manufacture of a semiconductor device. The method includes receiving, at the electronic device, a computer-aided design (CAD) image for a lithography process of the semiconductor device, and generating, at the electronic device, a first scanning electron microscope (SEM) image and a first segment (SEG) image from the CAD image by using a machine learning-based module, and the first SEG image includes information about a location of a defect.

公开(公告)号：US12062164B2

公开(公告)日：2024-08-13

申请号：US17547503

申请日：2021-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Cheol Kang ,  Dong Hoon Kuk

IPC: G06T7/00 ,  G06T5/70 ,  G06T7/13 ,  G06T7/30

CPC classification number: G06T7/0004 ,  G06T5/70 ,  G06T7/13 ,  G06T7/30 ,  G06T2207/10061

Abstract: A method of manufacturing a semiconductor device that includes providing a substrate having a pattern formed thereon. A scanning electron microscope (SEM) image is generated that includes a boundary image showing an edge of the pattern. A blended image is generated by performing at least one blending operation on the SEM image and a background image aligned with the boundary image. Contour data is generated by binarizing the blended image on a basis of a threshold value. The threshold value is determined by a critical dimension of the pattern.

公开(公告)号：US12118708B2

公开(公告)日：2024-10-15

申请号：US17465179

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Cheol Kang ,  Do-Nyun Kim ,  Jaehoon Kim ,  Woojoo Sim

IPC: G06T7/00 ,  G06N3/045

CPC classification number: G06T7/0006 ,  G06T7/97 ,  G06T2207/10061 ,  G06T2207/20081 ,  G06T2207/20221 ,  G06T2207/30148

Abstract: Disclosed is a wafer defect inference system, which includes a test equipment that receives a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit pattern on the semiconductor wafer and combines the first image and the second image to generate a combination image, and at least one computing device that is capable of communicating with the test equipment and infers a defect associated with the circuit pattern formed on the semiconductor wafer. The computing device receives the combination image, performs machine learning for inferring the defect based on the combination image, and generates an output image including information about the defect based on the machine learning.

公开(公告)号：US11714347B2

公开(公告)日：2023-08-01

申请号：US17245947

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo Yong Lee ,  Min-Cheol Kang ,  U Seong Kim ,  Seung Hune Yang ,  Jee Yong Lee

IPC: G03F1/36 ,  G03F1/76 ,  G06T3/40 ,  G06T7/00 ,  G06F30/3323 ,  G06F30/392

CPC classification number: G03F1/36 ,  G03F1/76 ,  G06F30/3323 ,  G06F30/392 ,  G06T3/4046 ,  G06T7/0006 ,  G06T2207/20084 ,  G06T2207/30148

Abstract: A process proximity correction method is performed by a process proximity correction computing device which performs a process proximity correction (PPC) through at least one of a plurality of processors. The process proximity correction method includes: converting a target layout including a plurality of patterns into an image, zooming-in or zooming-out the image at a plurality of magnifications to generate a plurality of input channels, receiving the plurality of input channels and performing machine learning to predict an after-cleaning image (ACI), comparing the predicted after-cleaning image with a target value to generate an after-cleaning image error, and adjusting the target layout on the basis of the after-cleaning image error.