Device and method for detecting defects on wafer

    公开(公告)号:US12118708B2

    公开(公告)日:2024-10-15

    申请号:US17465179

    申请日:2021-09-02

    IPC分类号: G06T7/00 G06N3/045

    摘要: Disclosed is a wafer defect inference system, which includes a test equipment that receives a first image obtained by imaging circuit patterns formed on a semiconductor wafer by using a scanning electron microscope and a second image obtained by imaging a layout image of a mask for implementing the circuit pattern on the semiconductor wafer and combines the first image and the second image to generate a combination image, and at least one computing device that is capable of communicating with the test equipment and infers a defect associated with the circuit pattern formed on the semiconductor wafer. The computing device receives the combination image, performs machine learning for inferring the defect based on the combination image, and generates an output image including information about the defect based on the machine learning.

    MAGNETIC MEMORY DEVICES
    3.
    发明申请

    公开(公告)号:US20220158085A1

    公开(公告)日:2022-05-19

    申请号:US17358435

    申请日:2021-06-25

    摘要: A magnetic memory device including a magnetic tunnel junction is provided. The magnetic tunnel junction includes a fixed layer, a polarization enhancement structure on the fixed layer, a tunnel barrier layer on the polarization enhancement structure, and a free layer on the tunnel barrier layer, wherein the polarization enhancement structure includes a plurality of polarization enhancement layers and at least one spacer layer which separates the plurality of polarization enhancement layers from each other. A thickness of each of the plurality of polarization enhancement layers is from 5 Å to about 20 Å, and a thickness of the at least one spacer layer is from about 2 Å to about 15 Å.

    Semiconductor devices
    4.
    发明授权

    公开(公告)号:US11270992B2

    公开(公告)日:2022-03-08

    申请号:US16992422

    申请日:2020-08-13

    摘要: A semiconductor device includes standard cells disposed in a first direction parallel to an upper surface of a substrate and a second direction intersecting the first direction, each standard cell including an active region, a gate structure disposed to intersect the active region, source/drain regions on the active region at both sides of the gate structure, and first interconnection lines electrically connected to the active region and the gate structures; filler cells disposed between at least portions of the standard cells, each filler cell including a filler active region and a filler gate structure disposed to intersect the filler active region; and a routing structure disposed on the standard cells and the filler cells and including second interconnection lines electrically connecting the first interconnection lines of different standard cells to each other, wherein the second interconnection lines includes a first line having a first width and a second line having a second width larger than the first width.

    System-on-chip including dynamic power monitor and frequency controller and operating method thereof

    公开(公告)号:US11709524B2

    公开(公告)日:2023-07-25

    申请号:US17736612

    申请日:2022-05-04

    IPC分类号: G06F1/08 H03K19/20

    CPC分类号: G06F1/08 H03K19/20

    摘要: A system-on-chip includes: a dynamic power monitor configured to generate a power detection signal by calculating an amount of power consumed by a functional circuit in real time; a frequency controller configured to detect an idle period and a running period of the functional circuit in response to the power detection signal, and generate a clock control signal based on the power detection signal; and a clock controller configured to change a frequency of a clock signal provided to the functional circuit, based on the clock control signal. The running period includes: a first running period in which the frequency of the clock signal has a first value based on the clock control signal; and a second running period in which the frequency of the clock signal has a second value that is greater than the first value based on the clock control signal.