公开(公告)号：US20240030089A1

公开(公告)日：2024-01-25

申请号：US18475926

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/563 ,  H01L24/16 ,  H01L25/18 ,  H01L25/0655 ,  H01L23/3185 ,  H01L2924/3025 ,  H01L2224/16227 ,  H01L2924/1616 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/30111

Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

公开(公告)号：US12176262B2

公开(公告)日：2024-12-24

申请号：US18475926

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/18

Abstract: A method of manufacturing a semiconductor package is provided and includes: forming a lower redistribution structure, the lower redistribution structure including lower redistribution patterns having lower connection pads; forming an upper redistribution structure on a boundary surface of the lower redistribution structure, the upper redistribution structure including upper redistribution patterns having upper connection pads electrically connected to the lower connection pads; forming openings exposing at least a portion of each of the lower connection pads; disposing an interposer substrate, including the lower redistribution structure and the upper redistribution structure, on a base substrate, the lower connection pads of the interposer substrate electrically connected to wiring patterns of the base substrate through lower connection bumps disposed on the openings; and disposing at least one of semiconductor chips, including connection pads, on the interposer substrate, the connection pads electrically connected to the upper connection pads through upper connection bumps.

公开(公告)号：US11798862B2

公开(公告)日：2023-10-24

申请号：US17354291

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok Cho ,  Minjeong Gu ,  Joonsung Kim ,  Jaehoon Choi

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1616 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/30111

Abstract: A semiconductor package includes a base substrate including a wiring pattern, an interposer substrate including lower and upper redistribution patterns, a semiconductor structure, a heat dissipation structure, a plurality of external connection bumps disposed on a lower surface of the base substrate, a plurality of lower connection bumps disposed between the base substrate and the interposer substrate, and a plurality of upper connection bumps disposed between the interposer substrate and the semiconductor structure.