公开(公告)号：US12237324B2

公开(公告)日：2025-02-25

申请号：US18052726

申请日：2022-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jangeun Lee ,  Minjoo Lee ,  Eunyoung Lee ,  Minsik Kim

IPC: H10B12/00 ,  H01L21/02 ,  H01L27/06

Abstract: An integrated circuit device according may include a plurality of gate structures embedded in a substrate, a direct contact on the substrate between the plurality of gate structures, and a bit line electrode layer on the direct contact. The bit line electrode layer has a thickness of about 10 nm to 30 nm. The bit line electrode layer may include a molybdenum tungsten (MoW) alloy including molybdenum (Mo) a range of about 25 at % to about 75 at %.

公开(公告)号：US20220230956A1

公开(公告)日：2022-07-21

申请号：US17535818

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Euibok Lee ,  Wandon Kim ,  Minjoo Lee ,  Hyunbae Lee

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole.

公开(公告)号：US09755026B2

公开(公告)日：2017-09-05

申请号：US15132800

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Su Yoo ,  WeonHong Kim ,  Moonkyun Song ,  Minjoo Lee ,  Soojung Choi

IPC: H01L29/40 ,  H01L29/423 ,  H01L21/441 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/441 ,  H01L21/762 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.