公开(公告)号：US20180151376A1

公开(公告)日：2018-05-31

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

公开(公告)号：US09525042B2

公开(公告)日：2016-12-20

申请号：US14700346

申请日：2015-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/28 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

公开(公告)号：US09064723B2

公开(公告)日：2015-06-23

申请号：US13751731

申请日：2013-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/788 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。

公开(公告)号：US08912611B2

公开(公告)日：2014-12-16

申请号：US14190346

申请日：2014-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： WeonHong Kim ,  Dae-Kwon Joo ,  Hajin Lim ,  Jinho Do ,  Kyungil Hong ,  Moonkyun Song

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/512 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.

Abstract translation: 制造半导体器件的方法包括在半导体层上形成下界面层，下界面层为氮化物层，在下界面层上形成中间界面层，中间界面层为氧化物层，形成 中间界面层上的高k电介质层。 高k电介质层的介电常数高于下界面层和中间界面层的介电常数。

公开(公告)号：US10217640B2

公开(公告)日：2019-02-26

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/51 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

公开(公告)号：US09755026B2

公开(公告)日：2017-09-05

申请号：US15132800

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Su Yoo ,  WeonHong Kim ,  Moonkyun Song ,  Minjoo Lee ,  Soojung Choi

IPC: H01L29/40 ,  H01L29/423 ,  H01L21/441 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/441 ,  H01L21/762 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.

公开(公告)号：US20150311310A1

公开(公告)日：2015-10-29

申请号：US14700346

申请日：2015-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOKJUN WON ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。

公开(公告)号：US09142461B2

公开(公告)日：2015-09-22

申请号：US14289076

申请日：2014-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinho Do ,  Hajin Lim ,  WeonHong Kim ,  Kyungil Hong ,  Moonkyun Song

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L21/26506 ,  H01L21/28185 ,  H01L21/2822 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

Abstract translation: 准备包括NMOS晶体管区域和PMOS晶体管区域的衬底。 在PMOS晶体管区域上形成硅 - 锗层。 氮原子注入硅 - 锗层的上部。 在NMOS晶体管区域和PMOS晶体管区域上形成第一栅极电介质层。 在形成第一栅极电介质层之前，将氮原子注入硅 - 锗层的上部。

公开(公告)号：US20130299916A1

公开(公告)日：2013-11-14

申请号：US13751731

申请日：2013-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L27/088

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.