公开(公告)号：US11120792B2

公开(公告)日：2021-09-14

申请号：US16296467

申请日：2019-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyun Kim ,  Gajin Song ,  Dongho Jang ,  Sangwook Kang ,  Hyunwoo Kang ,  Soojung Choi

IPC: G10L15/22 ,  G06F3/16 ,  G10L15/26 ,  H04W4/14 ,  G10L13/00

Abstract: An electronic device and method are disclosed. The electronic device includes a communication interface, a microphone, a speaker, a processor and a memory. The processor executes the method, including receiving a first message through a communication interface from an external device, in response to receiving a first user input associated with the first message through an input interface including a microphone, converting first text included in the first message into speech, outputting the speech through an output interface of the electronic device including a speaker, determining whether to execute an additional operation associated with the first message, based on at least one of a state of the first electronic device, the first message, and a second user input received via the microphone, and initiate a conversational mode for executing the additional operation based at least partly on the determination.

公开(公告)号：US10217640B2

公开(公告)日：2019-02-26

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/51 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

公开(公告)号：US09755026B2

公开(公告)日：2017-09-05

申请号：US15132800

申请日：2016-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Su Yoo ,  WeonHong Kim ,  Moonkyun Song ,  Minjoo Lee ,  Soojung Choi

IPC: H01L29/40 ,  H01L29/423 ,  H01L21/441 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/321

CPC classification number: H01L29/401 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/441 ,  H01L21/762 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of forming a semiconductor device includes forming a sacrificial gate pattern on an active pattern, forming spacers on opposite sidewalls of the sacrificial gate pattern, forming an interlayer insulating layer on the active pattern and the spacers, removing the sacrificial gate pattern to form a gate trench that exposes a region of the active pattern, forming a gate dielectric layer on the region of the active pattern exposed by the gate trench, performing a first heat treatment at a pressure of less than 1 atm to remove impurities in the interlayer insulating layer, performing a second heat treatment on the gate dielectric layer at a temperature greater than a temperature of the first heat treatment, and forming a gate electrode in the gate trench.

公开(公告)号：US20180151376A1

公开(公告)日：2018-05-31

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L21/3105

CPC classification number: H01L21/28185 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.