公开(公告)号：US20200293452A1

公开(公告)日：2020-09-17

申请号：US16814236

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO,LTD

Inventor： SUKHAN LEE ,  SHINHAENG KANG ,  NAMSUNG KIM

IPC: G06F12/0875 ,  G06N3/08 ,  G06F9/30

Abstract: A memory device includes a memory bank including one or more bank arrays, a PIM circuit configured to perform an operation logic processing operation, and an instruction memory including first to mth instruction queue segments configured in a circular instruction queue to store instructions provided by a host, where instructions stored in the first to mth instruction queue segments are executed in response to an operation request from the host and each new instruction provided by the host is updated over a completely executed instruction in the circular instruction queue.

公开(公告)号：US20200294575A1

公开(公告)日：2020-09-17

申请号：US16810344

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEONGIL O ,  SHINHAENG KANG ,  NAMSUNG KIM ,  KYOMIN SOHN ,  SUKHAN LEE

IPC: G11C11/4096 ,  G06F13/16 ,  G06N3/04 ,  G06N3/063

Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

公开(公告)号：US20250147728A1

公开(公告)日：2025-05-08

申请号：US18668411

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEWON PARK ,  SHINHAENG KANG ,  KYOMIN SOHN

IPC: G06F7/544 ,  G06F7/501

Abstract: A memory device includes a memory cell array; and a processing in memory (PIM) unit including a plurality of multiplication and accumulation (MAC) operators which is configured to perform multiply-accumulation operations based on data stored in the memory cell array. The plurality of MAC operators performs the multiply-accumulation operations based on the data in a first stage, and to perform partial sum operations based on result values of the multiply-accumulation operations in a second stage.

公开(公告)号：US20230236836A1

公开(公告)日：2023-07-27

申请号：US18194174

申请日：2023-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUKHAN LEE ,  SHINHAENG KANG ,  NAMSUNG KIM ,  SEONGIL O ,  HAK-SOO YU

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F15/7821

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.