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公开(公告)号：US11805641B2
公开(公告)日：2023-10-31
申请号：US17568499
申请日：2022-01-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sa Hwan Hong , Jong Myeong Kim , Myeong Jin Bang , Kong Soo Lee , Han Mei Choi , Ho Kyun An
Abstract: A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device comprises providing a first substrate including a buffer layer and a base substrate, forming a stacked mold structure including a plurality of unit laminates on the buffer layer, each of the unit laminates including a first sacrificial layer, a first silicon layer, a second sacrificial layer, and a second silicon layer sequentially stacked in a vertical direction and replacing the stacked mold structure with a stacked memory structure through a replacement process, wherein the stacked memory structure includes a metal pattern which replaces the first sacrificial layer and the second sacrificial layer, and an insulating pattern which replaces the second silicon layer, the buffer layer includes silicon-germanium, and a germanium concentration of the buffer layer varies depending on the germanium concentration of the first sacrificial layer and the germanium concentration of the second sacrificial layer.
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公开(公告)号：US11521902B2
公开(公告)日：2022-12-06
申请号：US17032085
申请日：2020-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sa Hwan Hong , Yong Hee Park , Kang Ill Seo
IPC: H01L29/66 , H01L21/8238 , H01L21/308
Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.
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Patent Agency Ranking
公开(公告)号：US11233146B2
公开(公告)日：2022-01-25
申请号：US16828049
申请日：2020-03-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung Hyun Song , Chang Woo Sohn , Young Chai Jung , Sa Hwan Hong
Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.
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公开(公告)号：US20200020599A1
公开(公告)日：2020-01-16
申请号：US16434211
申请日：2019-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sa Hwan Hong , Yong Hee Park , Kang Ill Seo
IPC: H01L21/8238 , H01L29/66 , H01L21/308
Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.
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公开(公告)号：US11699754B2
公开(公告)日：2023-07-11
申请号：US17563608
申请日：2021-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seung Hyun Song , Chang Woo Sohn , Young Chai Jung , Sa Hwan Hong
CPC classification number: H01L29/7827 , H01L29/0653 , H01L29/401 , H01L29/42364 , H01L29/42368 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66666
Abstract: A vertical field-effect transistor (VFET) includes: a fin structure on a substrate; a gate structure including a gate dielectric layer on an upper portion of a sidewall of the fin structure, and a conductor layer on a lower portion of the gate dielectric layer; a top source/drain (S/D) region above the fin structure and the gate structure; a bottom S/D region below the fin structure and the gate structure; a top spacer on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.
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公开(公告)号：US11295986B2
公开(公告)日：2022-04-05
申请号：US16724702
申请日：2019-12-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min Gyu Kim , Sa Hwan Hong
IPC: H01L21/8234
Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the VFET devices are provided. The methods may include forming a first channel region and a second channel region on a substrate, forming a recess in the substrate between the first and second channel regions by removing a portion of the liner and a portion of the substrate, forming a bottom source/drain region in the recess of the substrate, forming a capping layer on the bottom source/drain region, removing the liner and the capping layer, forming a spacer on the substrate and the bottom source/drain region, and forming a gate structure on side surfaces of the first and second channel regions.
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公开(公告)号：US10818560B2
公开(公告)日：2020-10-27
申请号：US16434211
申请日：2019-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sa Hwan Hong , Yong Hee Park , Kang Ill Seo
IPC: H01L21/8238 , H01L29/66 , H01L21/308
Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.
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