公开(公告)号：US10650910B2

公开(公告)日：2020-05-12

申请号：US16249543

申请日：2019-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwook Jeong ,  Sanghoon Myung ,  Min-Chul Park ,  Jeonghoon Ko ,  Jisu Ryu ,  Hyunjae Jang ,  Hyungtae Kim ,  Yunrong Li ,  Min Chul Jeon

IPC: G11C7/00 ,  G11C29/50 ,  G11C29/48 ,  G11C29/56 ,  G01R31/27 ,  G01R31/3185 ,  G01R31/30 ,  G01R31/26

Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

公开(公告)号：US20210056425A1

公开(公告)日：2021-02-25

申请号：US16910908

申请日：2020-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changwook JEONG ,  Sanghoon Myung ,  In Huh ,  Hyeonkyun Noh ,  Minchul Park ,  Hyunjae Jang

IPC: G06N3/08 ,  G06N20/00 ,  G06K9/62

Abstract: A method for a hybrid model that includes a machine learning model and a rule-based model, includes obtaining a first output from the rule-based model by providing a first input to the rule-based model, and obtaining a second output from the machine learning model by providing the first input, a second input, and the obtained first output to the machine learning model. The method further includes training the machine learning model, based on errors of the obtained second output.

公开(公告)号：US11982980B2

公开(公告)日：2024-05-14

申请号：US17230275

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Kim ,  Sanghoon Myung ,  Wonik Jang ,  Yongwoo Jeon ,  Kanghyun Baek ,  Jisu Ryu ,  Changwook Jeong

IPC: G05B13/04 ,  G05B13/02 ,  G06N3/045 ,  H01L27/02

CPC classification number: G05B13/042 ,  G05B13/027 ,  G06N3/045 ,  H01L27/0207

Abstract: According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

公开(公告)号：US11886783B2

公开(公告)日：2024-01-30

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Myung ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06F30/398 ,  G06N3/044 ,  G06N3/08 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US20250028954A1

公开(公告)日：2025-01-23

申请号：US18768183

申请日：2024-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Myung ,  Kyeyeop Kim ,  Jaehoon Jeong ,  Yunji Choi ,  Songyi Han

IPC: G06N3/08

Abstract: A method of generating a neural network model and performing a circuit simulation by using the neural network model is presented. The method includes generating sample data by performing a process simulation based on a temperature and a process parameter, training the neural network model based on the sample data, performing a lightweight operation on the neural network model to generate a lightweight neural network model, re-training the lightweight neural network model, and performing the circuit simulation with the process parameter as an input by using the re-trained lightweight neural network model.

公开(公告)号：US11775840B2

公开(公告)日：2023-10-03

申请号：US16909132

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonik Jang ,  Sanghoon Myung ,  Changwook Jeong ,  Sunghee Lee

IPC: G06N3/088 ,  G06N3/045

CPC classification number: G06N3/088 ,  G06N3/045

Abstract: A non-transitory computer-readable medium storing a program code including an image generation model, which when executed, causes a processor to input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies, and to input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.

公开(公告)号：US11574095B2

公开(公告)日：2023-02-07

申请号：US16906038

申请日：2020-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Myung ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06N3/04 ,  G06F30/398

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.