Abstract:
According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.
Abstract:
An electronic device is provided. The electronic device includes a housing including a window, configured to form a 1st side of the electronic device, and a 2nd side of the electronic device directed in an opposite direction of the 1st side of the electronic device, a circuit board between the 1st side and the 2nd side of the electronic device, and including an input circuit configured to detect an input based on a change in a capacitance, a spacer between the window and the circuit board, and having at least one space formed on one side facing the circuit board, a contact electrically connected to the input circuit by being mounted to one side of the circuit board, and contained in the at least one space, and a conductive plate coupled to the spacer, and electrically connected to the contact through the at least one space.
Abstract:
A surface treatment method of an electronic device is provided. The surface treatment method includes processing a first pattern on a surface of a top mold and a second pattern on a surface of a bottom mold, coating a Ultra-Violet (UV) molding liquid on each of a front surface of a raw sheet material and the bottom mold facing a rear surface of the raw sheet material raw, positioning the raw sheet material between the top mold and the bottom mold, pressing the top mold and the bottom mold to each other, curing the UV molding liquid, and separating the raw sheet material from the top mold and the bottom mold and forming a print layer on the front surface and the rear surface of the raw sheet material.
Abstract:
A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor product based on the plurality of process policies.
Abstract:
Example embodiments relate to a lateral type photodiode including a substrate, an insulation mask layer formed on the substrate, and a first type semiconductor layer, an active layer, and a second type semiconductor layer that contact a surface of the insulation mask layer and that are sequentially disposed in a direction substantially parallel to the surface of the insulation mask layer. The insulation mask layer includes a through hole, and the first type semiconductor layer, the active layer, and the second type semiconductor layer are sequentially formed from the through hole by using a lateral overgrowth method.
Abstract:
A semiconductor protection device includes: an N-type epitaxial layer, a device isolation layer disposed in the N-type epitaxial layer, an N-type drift region disposed below the device isolation layer, an N-type well disposed in the N-type drift region, first and second P-type drift regions, respectively disposed to be in contact with the device isolation layer, and spaced apart from the N-type drift region, first and second P-type doped regions, respectively disposed in the first and second P-type drift regions, first and second N-type floating wells, respectively disposed in the first and second P-type drift regions to be spaced apart from the first and second P-type doped regions, and disposed to be in contact with the device isolation layer, and first and second contact layer, respectively disposed to cover the first and second N-type floating well, to be in contact with the device isolation layer.
Abstract:
A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product, generating first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained through machine learning based on training data including TCAD simulation data, generating second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model generated based on information of measurement of at least one semiconductor characteristic of a first semiconductor product, generating, based on the first semiconductor characteristic data and the second semiconductor characteristic data, a plurality of process policies respectively corresponding to a plurality of strategic references, by using a plurality of strategy models; and providing a final process policy corresponding to the target semiconductor product based on the plurality of process policies.
Abstract:
A semiconductor device with fin capacitors is disclosed. The device includes a substrate including a first region and a second region; first and second active fins at the first and second regions, respectively, of the substrate; a device isolation layer in a first trench between the first active fins; first and second gate electrodes that cross the first and second active fins, respectively; a first dielectric layer between the first active fins and the first gate electrode to extend along the first gate electrode, and a second dielectric layer between the second active fins and the second gate electrode to extend along the second gate electrode. The first dielectric layer is spaced apart from a bottom surface of the first trench by the device isolation layer between the bottom surface of the first trench and the first dielectric layer. The second dielectric layer is in direct contact with a bottom surface of a second trench between the second active fins.