公开(公告)号：US11031410B2

公开(公告)日：2021-06-08

申请号：US16425365

申请日：2019-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jun Park ,  Min-Tai Yu ,  Jae Duk Lee

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06

Abstract: A nonvolatile memory device in which reliability is improved and a method for fabricating the same are provided. The nonvolatile memory device includes a mold structure which includes a first insulating pattern, a first gate electrode and a second insulating pattern sequentially stacked on a substrate, a semiconductor pattern which penetrates the mold structure, is connected to the substrate, and extends in a first direction, a first charge storage film extending in the first direction between the first insulating pattern and the second insulating pattern and between the first gate electrode and the semiconductor pattern, and a blocking insulation film between the first gate electrode and the first charge storage film, wherein a first length at which the first charge storage film extends in the first direction is longer than a second length at which the blocking insulation film extends in the first direction.

公开(公告)号：US12154632B2

公开(公告)日：2024-11-26

申请号：US18545144

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Lee ,  Jin-Kyu Kang ,  Rae Young Lee ,  Se Jun Park ,  Jae Duk Lee ,  Gu Yeon Han

IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

公开(公告)号：US11881268B2

公开(公告)日：2024-01-23

申请号：US17712238

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ji Lee ,  Jin-Kyu Kang ,  Rae Young Lee ,  Se Jun Park ,  Jae Duk Lee ,  Gu Yeon Han

IPC: G11C16/16 ,  G11C16/04 ,  G11C11/56 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

公开(公告)号：US11538533B2

公开(公告)日：2022-12-27

申请号：US17233858

申请日：2021-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gu Yeon Han ,  Jin-Kyu Kang ,  Rae Young Lee ,  Se Jun Park ,  Jae Duk Lee

IPC: G11C7/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C16/30 ,  G11C16/24 ,  G11C16/32

Abstract: A non-volatile memory device including: a memory cell array including non-volatile memory blocks connected to a plurality of word lines, a plurality of bit lines and a common source line; a common source line driver configured to supply a common source line voltage to the common source line; a page buffer unit configured to supply a bit line voltage to at least one of the plurality of bit lines; a control logic circuit configured to adjust the common source line voltage and the bit line voltage; and a channel initialization circuit, wherein the channel initialization circuit sets the common source line voltage and the bit line voltage to an initialization pulse, and the channel initialization circuit applies the initialization pulse between a plurality of read sections in which a read voltage is applied to at least two of the plurality of word lines.

公开(公告)号：US09853045B2

公开(公告)日：2017-12-26

申请号：US15173888

申请日：2016-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Hwang ,  Jang Gn Yun ,  Ahn Sik Moon ,  Se Jun Park ,  Zhiliang Xia ,  Joon Sung Lim

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.