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公开(公告)号：US20230422502A1
公开(公告)日：2023-12-28
申请号：US18202111
申请日：2023-05-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seulji LEE , Jinhyuk Kim , Byoungil Lee , Sehoon Lee , Jinwoo Jeon
Abstract: A semiconductor device includes: a memory cell structure on a peripheral circuit structure; a through wiring region on the peripheral circuit structure; and a barrier structure surrounding the through wiring region. The memory cell structure includes: gate electrodes and first interlayer insulating layers that are alternately stacked, the gate electrodes forming a step shape on the second region; a channel structure; and isolation regions penetrating through the gate electrodes. The through wiring region includes: second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region; and a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices. Each of the sacrificial insulating layers includes a recess portion that is horizontally recessed from the barrier structure toward each of the sacrificial insulating layers.
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公开(公告)号：US20230217660A1
公开(公告)日：2023-07-06
申请号：US18062837
申请日：2022-12-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoungil LEE , Sehoon Lee
IPC: H01L29/76
CPC classification number: H01L27/11582 , H01L27/11556 , H01L27/11529 , H01L27/11573
Abstract: A semiconductor device includes a lower structure, stack structure including gate electrodes stacked and spaced apart from each other on a first region of the lower structure and extending in a staircase shape on a second region of the lower structure, and interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes on the first region, and isolation structures penetrating through the gate electrodes spaced apart from each other. Each channel structure a channel bent portion between first and second channel structures. Each isolation structure includes a first isolation bent portion between first and second isolation structures and a second isolation bent portion between second and third isolation structures. A width of an upper surface of the second isolation structure is narrower than a width of a lower surface of the third isolation structure.
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公开(公告)号：US20250120080A1
公开(公告)日：2025-04-10
申请号：US18666888
申请日：2024-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Bumkyu Kang , Sehoon Lee , Sukkang Sung
Abstract: A semiconductor device includes a first substrate structure, and a second substrate structure connected to the first substrate structure and including circuit elements and second bonding metal layers. The first substrate structure includes gate electrodes stacked along a first direction, a supporter layer on the gate electrodes, channel structures extending along the first direction while penetrating the gate electrodes, separation regions extending in the first direction and a second direction by penetrating through the gate electrodes, and first bonding metal layers connected to the second bonding metal layers. The separation regions respectively include first regions spaced apart from each other along the second direction and a second region surrounding side surfaces of the first regions and extending in the second direction. The first regions and the channel structures penetrate the supporter layer, and a portion of a lower surface of the supporter layer is in contact with the second region.
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Patent Agency Ranking
公开(公告)号：US20250126790A1
公开(公告)日：2025-04-17
申请号：US18756161
申请日：2024-06-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Minyong Lee , Jiyoung Kim , Sehoon Lee , Junhyoung Kim , Sukkang Sung
Abstract: An example non-volatile memory device includes a substrate including a first cell region, a second cell region, and a connection region between the first cell region and the second cell region, a mold structure including a plurality of gate electrodes being stacked in a stepped pattern in a pad region, a trench along a profile of the mold structure on the pad region, the trench including a bottom surface having a stair shape and a first sidewall on a boundary between the pad region and a wall region, a liner film on the first sidewall of the trench, a recess in the trench and exposing a pad portion of a gate electrode, a cell contact provided at the recess and connected with the pad portion, and a cover insulating layer provided at the trench. The liner film has a different etch selectivity with respect to the cover insulating layer.
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公开(公告)号：US20220115390A1
公开(公告)日：2022-04-14
申请号：US17377840
申请日：2021-07-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehoon Lee , Byoungil Lee
IPC: H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L27/11539 , H01L23/522
Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.
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公开(公告)号：US20250120089A1
公开(公告)日：2025-04-10
申请号：US18830677
申请日：2024-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sehoon Lee , Minyong Lee , Junhyoung Kim , Jiyoung Kim , Sukkang Sung
IPC: H10B43/40 , G11C16/04 , H01L23/00 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
Abstract: A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit, and a lower insulating structure on the peripheral circuit, a cell array structure having a cell area and a peripheral connection area and including an upper insulating structure in contact with the lower insulating structure, a cell stack in the cell area on the upper insulating structure, a common source line layer on the cell stack and having a common source opening, a plurality of cell channel structures extending in a vertical direction in the cell stack and into the common source line layer, and a support structure extending in the vertical direction in the cell stack and into the common source opening, and a pad pattern extending from the peripheral connection area to the cell area on the cell array structure and overlapping the support structure in the vertical direction.
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公开(公告)号：US20250081472A1
公开(公告)日：2025-03-06
申请号：US18766970
申请日：2024-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sehoon Lee , Joonyoung Kwon , Junhyoung Kim , Sukkang Sung
Abstract: A non-volatile memory device includes a substrate, a first semiconductor layer including a memory cell array on the substrate, a second semiconductor layer including a peripheral circuit that is configured to write data to or read the data from the memory cell array, where the second semiconductor layer is on the first semiconductor layer, and a protrusion structure including a wire that extends into at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer, where the protrusion structure extends from a first surface of the first semiconductor layer and from a first surface of the second semiconductor layer, and where the protrusion structure extends in a second direction that is perpendicular to the first direction.
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公开(公告)号：US12225730B2
公开(公告)日：2025-02-11
申请号：US17377840
申请日：2021-07-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehoon Lee , Byoungil Lee
IPC: H10B43/35 , H01L23/522 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/46 , H10B43/10 , H10B43/27 , H10B43/40
Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.
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