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公开(公告)号：US20250048631A1
公开(公告)日：2025-02-06
申请号：US18664690
申请日：2024-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jiyoung Kim , Junhyoung Kim , Joonyoung Kwon , Siwan Kim , Sukkang Sung
Abstract: A semiconductor memory device including a cell array structure and a peripheral circuit structure is provided. The cell array structure includes a first stack structure, a second stack structure on the first stack structure, and a third stack structure on the second stack structure, each of the first to third stack structures including a plurality of word lines, vertical channel structures extending into the first to third stack structures, and a second cell contact plug extending into the first to third stack structures and connected to a second contact plug at an end of a second word line in the second stack structure. The second cell contact plug includes a first horizontal protrusion having a horizontal width that increases discontinuously at a connection portion of the first stack structure and the second stack structure.
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公开(公告)号：US20240397715A1
公开(公告)日：2024-11-28
申请号：US18544735
申请日：2023-12-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Joonyoung Kwon , Junhyoung Kim , Jiyoung Kim , Sukkang Sung
IPC: H10B43/27 , G11C16/04 , H01L23/522 , H01L23/528 , H01L25/065 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/35 , H10B43/40 , H10B80/00
Abstract: A semiconductor device including a substrate having a cell array region and a contact region, a gate stack structure positioned in the cell array region, and including a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked on the substrate, a gate pattern stack structure positioned in the contact region, and including a plurality of gate patterns extending from the plurality of gate electrodes, and a plurality of insulation layers alternately stacked with the plurality of gate patterns, a channel structure penetrating the gate stack structure and extending in a direction crossing or intersecting the substrate, and a gate contact portion in the contact region, and penetrating at least a portion of the gate pattern stack structure to be electrically connected to the gate pattern, the plurality of insulation layers including a first insulation layer and a second insulation layer, the second insulating layer including a material different from a material included in the first insulation layer.
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Patent Agency Ranking
公开(公告)号：US20240107767A1
公开(公告)日：2024-03-28
申请号：US18463620
申请日：2023-09-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Joonyoung Kwon , Jiyoung Kim , Jinhyuk Kim , Sukkang Sung
IPC: H10B43/27
CPC classification number: H10B43/27
Abstract: A semiconductor device includes a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure includes gate electrodes stacked in a first direction and extending in a second direction. The first division pattern extends in the second direction through the gate electrode structure, and divides the gate electrode structure in a third direction. The memory channel structure extends through the gate electrode structure, and includes a channel and a charge storage structure. The first division pattern includes first and second sidewalls opposite to each other in the third direction. First recesses are spaced apart from each other in the second direction on the first sidewall, and second recesses are spaced apart from each other in the second direction on the second sidewall. The first and second recesses do not overlap in the third direction.
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公开(公告)号：US20240099012A1
公开(公告)日：2024-03-21
申请号：US18308222
申请日：2023-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joonyoung Kwon , Jiyoung Kim , Junhyoung Kim , Sukkang Sung
Abstract: A semiconductor device includes a peripheral circuit structure including a plurality of circuit areas, a cell array structure including a pair of memory cell blocks overlapping the peripheral circuit structure in a first direction and spaced apart in a second direction, perpendicular to the first direction, with a peripheral circuit connection area therebetween, a first circuit area of the plurality of circuit areas that overlaps the peripheral circuit connection area in the first direction, and at least one contact plug extending in the first direction from the peripheral circuit connection area, and including a first end portion configured to connect to at least one circuit included in the first circuit area and facing the first circuit area and a second end portion configured to connect to an external connection terminal.
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公开(公告)号：US20250081472A1
公开(公告)日：2025-03-06
申请号：US18766970
申请日：2024-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sehoon Lee , Joonyoung Kwon , Junhyoung Kim , Sukkang Sung
Abstract: A non-volatile memory device includes a substrate, a first semiconductor layer including a memory cell array on the substrate, a second semiconductor layer including a peripheral circuit that is configured to write data to or read the data from the memory cell array, where the second semiconductor layer is on the first semiconductor layer, and a protrusion structure including a wire that extends into at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer, where the protrusion structure extends from a first surface of the first semiconductor layer and from a first surface of the second semiconductor layer, and where the protrusion structure extends in a second direction that is perpendicular to the first direction.
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公开(公告)号：US20250063729A1
公开(公告)日：2025-02-20
申请号：US18666514
申请日：2024-05-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhyoung Kim , Joonyoung Kwon , Siwan Kim , Jiyoung Kim , Sukkang Sung
Abstract: A semiconductor device includes a plate layer; conductive layers spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer, extending by different lengths in a second direction perpendicular to the first direction, and forming a staircase region; a gap-fill insulating layer on the staircase region; and vertical structures penetrating through the gap-fill insulating layer and the conductive layers in the staircase region and extending in the first direction, and wherein the gap-fill insulating layer includes voids disposed symmetrically with respect to at least one of the vertical structures or a center of the staircase region in a third direction perpendicular to the first direction and the second direction.
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公开(公告)号：US20240079323A1
公开(公告)日：2024-03-07
申请号：US18350999
申请日：2023-07-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joonyoung Kwon , Dawoon Jeong , Jiyoung Kim , Sukkang Sung , Woosung Yang
IPC: H01L23/528 , G11C5/06 , H01L25/065 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40 , H10B80/00
CPC classification number: H01L23/5283 , G11C5/063 , H01L25/0655 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40 , H10B80/00
Abstract: A semiconductor device includes a first conductive plate structure and a second conductive plate structure, arranged at a same vertical level on a semiconductor chip and horizontally spaced apart from each other on the semiconductor chip, a first structure on the first conductive plate structure and including first separation structures and first memory blocks, and a second structure on the second conductive plate structure and including second separation structures and second memory blocks. The first memory blocks are spaced apart from each other by the first separation structures, and extend in parallel to each other in a first horizontal direction. The second memory blocks are spaced apart from each other by the second separation structures, and extend in parallel to each other in a second horizontal direction. The first and second horizontal directions are parallel to an upper surface of the first conductive plate structure, and are perpendicular to each other.
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