公开(公告)号：US20240153567A1

公开(公告)日：2024-05-09

申请号：US18209069

申请日：2023-06-13

Applicant: Samsung Electronics Co.,Ltd.

Inventor： Hyojin AHN ,  Seongkuk KIM ,  Dongwoo SHIN ,  Seoyeong LEE ,  Changjun LEE ,  Hoon JO

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3409 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: The present disclosure provides apparatuses and methods for operating a flash memory for programming operating system (OS) data before an surface mount technology (SMT) process. In some embodiments, the method includes erasing a plurality of memory cells in a memory block, reducing a lateral charge loss of the plurality of memory cells due to high temperature degradation during the SMT process by applying a pre-program voltage to word lines coupled to the memory block, and performing multi-bit programming of the OS data in the plurality of memory cells, prior to performing the SMT process. The applying of the pre-program voltage causes threshold voltages of the plurality of memory cells to increase.

公开(公告)号：US20250068333A1

公开(公告)日：2025-02-27

申请号：US18945678

申请日：2024-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojin AHN ,  Seoyeong LEE ,  Hoon JO

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B43/27

Abstract: In some embodiments, an operating method of a storage device includes obtaining a plurality of points by searching for a first valley point between threshold voltage distributions of selection memory cells coupled to a selection word line of a plurality of word lines; calculating, using a first function, a first voltage level that corresponds to a first reference count value; calculating, using a second function, a second voltage level that corresponds to the first reference count value; classifying the selection memory cells into a plurality of coupling patterns according to an aggressor cell group of each of adjacent memory cells coupled to at least one adjacent word line adjacent to the selection word line; and performing a read operation, based on the plurality of coupling patterns of the selection memory cells, the first voltage level, and the second voltage level.