公开(公告)号：US20200211646A1

公开(公告)日：2020-07-02

申请号：US16502744

申请日：2019-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sung CHO ,  Moo-Sung KIM ,  Seung-You BAEK ,  Jong-Min BAEK ,  Bong-Kil JUNG

IPC: G11C13/00

Abstract: In some example embodiments, a program pulse is applied to a resistive memory cell and a plurality of post pulses are applied to the resistive memory cell at a time point after a relaxation time from a time point when application of the program pulse is finished, the plurality of post pulses having voltage levels that increase sequentially. Programming speed and/or performance of the resistive memory device may be enhanced by accelerating resistance drift of the resistive memory cell using the plurality of post pulses having the voltage levels that increase sequentially.

公开(公告)号：US20200051628A1

公开(公告)日：2020-02-13

申请号：US16377420

申请日：2019-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-sung JOO ,  Seung-You BAEK ,  Ki-sung KIM

IPC: G11C13/00 ,  G06F11/07 ,  G11C11/56

Abstract: A memory controller may detect degradation in accordance with a bit error rate (BER) of the resistive memory device including memory cells. The memory controller may control the memory cells to be programmed to a first resistance state, read the programmed memory cells, and receive the BER of the memory cells generated during a read operation from the resistive memory device. The memory controller may determine a quantity of program cycles of the memory cells based on the BER. The quantity may be determined based on reference to a lookup table indicating a correlation between the BER and the quantity of program cycles.