Abstract:
A printed circuit board (PCB) for reducing a size of a semiconductor package and a semiconductor package including the same are provided. The PCB includes a substrate base including a chip attach area disposed on a top thereof, a top pad and a bottom pad respectively disposed on the top and a bottom of the substrate base, a first top solder resist layer formed on the top of the substrate base and including a first pad opening corresponding to the top pad and covering the chip attach area, a second top solder resist layer formed on the first top solder resist layer and including a second pad opening corresponding to the top pad and a chip attach opening corresponding to the chip attach area, and a bottom solder resist layer formed on the bottom of the substrate base and including a third pad opening corresponding to the bottom pad.
Abstract:
A thermoelectric material includes a stack structure including alternately stacked first and second material layers. The first material layer may include a carbon nano-material. The second material layer may include a thermoelectric inorganic material. The first material layer may include a thermoelectric inorganic material in addition to the carbon nano-material. The carbon nano-material may include, for example, graphene. At least one of the first and second material layers may include a plurality of nanoparticles. The thermoelectric material may further include at least one conductor extending in an out-of-plane direction of the stack structure.
Abstract:
A heat radiation-thermoelectric fin includes a thermoelectric inorganic material on a heterogeneous laminate of graphene. The heterogeneous laminate may be tube-shaped or plate-shaped, and a metal conductor may be coupled to one or more of the heterogeneous laminate. A thermoelectric module may be formed to include the fin, and a thermoelectric apparatus may include a heat supplier connected to the thermoelectric module.