公开(公告)号：US20130200524A1

公开(公告)日：2013-08-08

申请号：US13660584

申请日：2012-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Han ,  Hyun-Cheol Kim

IPC: H01L23/48

CPC classification number: H01L23/3107 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a semiconductor package may include providing a first package including a first semiconductor chip mounted on a first package substrate having a via-hole and molded by a first mold layer, providing a second package including a second semiconductor chip mounted on a second package substrate having a connection pad and molded by a second mold layer, stacking the first package on the second package to vertically align the via-hole with the connection pad, forming a through-hole penetrating the first and second packages and exposing the connection pad, and forming an electrical connection part in the through-hole. The electrical connection part may electrically connect the first package and the second package to each other.

Abstract translation: 形成半导体封装的方法可以包括提供第一封装，其包括安装在第一封装基板上的第一半导体芯片，该第一封装基板具有通孔并由第一模具层模制，提供包括安装在第二模具上的第二半导体芯片的第二封装 封装基板，具有连接焊盘并由第二模具层模制，将第一封装堆叠在第二封装上以将通孔垂直对准连接焊盘，形成贯穿第一和第二封装的通孔并暴露连接焊盘 并且在所述通孔中形成电连接部。 电连接部分可以将第一包装和第二包装彼此电连接。