公开(公告)号：US20250062229A1

公开(公告)日：2025-02-20

申请号：US18660743

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhee Lee ,  Chulmin Choi ,  Sangyong Park ,  Dajin Kim ,  Taeho Kim ,  Gunwook Yoon ,  Taehun Kim ,  Seungjae Baik ,  Jaeduk Lee

IPC: H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor structure that includes a first substrate, circuit devices on the first substrate, a lower interconnection structure, and a lower bonding structure; and a second semiconductor structure disposed on and connected to the first semiconductor structure The second semiconductor structure includes a stack structure; channel structures that including a first portion that penetrate through the stack structure in the vertical direction and a second portion that extends upward from the first portion; a first material layer disposed on the stack structure and the channel structure and having first conductivity; and a second material layer disposed between the first material layer and the stack structure and having second conductivity., The first material layer overlaps second portions of the channel structures in the vertical direction, and the second material layer does not overlap the second portions of the channel structures in the vertical direction.

公开(公告)号：USRE46389E1

公开(公告)日：2017-05-02

申请号：US14686984

申请日：2015-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

IPC: H01L21/8247 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

公开(公告)号：US20250040176A1

公开(公告)日：2025-01-30

申请号：US18629093

申请日：2024-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngtaek Oh ,  Jiwoong Kim ,  Taehun Kim ,  Minkyung Bae ,  Seungjae Baik ,  Jaeduk Lee ,  Doohee Hwang

IPC: H01L29/78 ,  H01L23/00 ,  H01L25/065 ,  H01L29/08 ,  H01L29/10 ,  H10B80/00

Abstract: A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure. The cell structure includes a plurality of gate electrodes spaced apart from each other in a vertical direction, a channel structure passing through the plurality of gate electrodes and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end, and a common source layer covering the second end of the channel structure. The channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region that contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.