公开(公告)号：US09997523B2

公开(公告)日：2018-06-12

申请号：US15631308

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L21/82 ,  H01L27/11 ,  H01L51/00 ,  H01L51/05 ,  H01L27/28

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

公开(公告)号：US20170294441A1

公开(公告)日：2017-10-12

申请号：US15631308

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L27/11 ,  H01L27/28 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

公开(公告)号：US12238931B2

公开(公告)日：2025-02-25

申请号：US17387868

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hwa Seo ,  Hakseon Kim ,  Sungkweon Baek

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a gate electrode on a semiconductor substrate, a gate insulating layer between the gate electrode and the semiconductor substrate, a first epitaxial layer disposed on the semiconductor substrate and at a side of the gate electrode, a second epitaxial layer disposed on the semiconductor substrate and at an opposite side of the gate electrode, a first contact plug in contact with a portion of the first epitaxial layer, and a second contact plug in contact with a portion of the second epitaxial layer. Top surfaces of the first and second epitaxial layers may be located at a level higher than a top surface of the gate electrode.

公开(公告)号：US09721957B2

公开(公告)日：2017-08-01

申请号：US14563695

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L27/11 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

公开(公告)号：US12010846B2

公开(公告)日：2024-06-11

申请号：US17476711

申请日：2021-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkweon Baek ,  Hakseon Kim ,  Jaehwa Seo

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A transistor of a semiconductor device includes an isolation region, an active region disposed in the isolation region, a gate extending in a second direction on the active region, and source and drain regions respectively extending in a first direction perpendicular to the second direction in the active region on first and second sides of the gate. The source and drain regions include low-concentration source and drain doping regions including first and second low-concentration source and drain doping regions The source and drain regions further include high-concentration source and drain doping regions respectively disposed in the low-concentration source and drain doping regions and having higher doping concentrations than the low-concentration source and drain doping regions. A first length in the second direction of the first low-concentration source and drain doping regions is greater than a second length in the second direction of the second low-concentration source and drain doping regions.

公开(公告)号：USRE46389E1

公开(公告)日：2017-05-02

申请号：US14686984

申请日：2015-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juwan Lim ,  Sungkweon Baek ,  Kwangmin Park ,  Seungjae Baik ,  Kihyun Hwang

IPC: H01L21/8247 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A nonvolatile memory device and a method of forming the nonvolatile memory device, the method including forming a tunnel insulating layer on a substrate, wherein forming the tunnel insulating layer includes forming a multi-element insulating layer by a process including sequentially supplying a first element source, a second element source, and a third element source to the substrate, forming a charge storage layer on the tunnel insulating layer, forming a blocking insulating layer on the charge storage layer, and forming a control gate electrode on the blocking insulating layer.

公开(公告)号：US20150179655A1

公开(公告)日：2015-06-25

申请号：US14563695

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Toshiro Nakanishi ,  Donghwan Kim ,  Suhwan Kim ,  Yubin Kim ,  Jin Soak Kim ,  Gabjin Nam ,  Sungkweon Baek ,  Taehyun An ,  Eunae Chung

IPC: H01L27/11 ,  H01L51/00 ,  H01L51/05 ,  H01L27/28

CPC classification number: H01L27/1104 ,  H01L27/281 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/057 ,  H01L51/0575

Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.

Abstract translation: 静态随机存取存储器（SRAM）单元可以包括第一上拉晶体管，第一下拉晶体管，第二上拉晶体管，第二下拉晶体管，第一存取晶体管和第二存取晶体管， 全部在6晶体管SRAM单元中耦合在一起，其中每个晶体管被配置为垂直沟道晶体管。

公开(公告)号：US11575009B2

公开(公告)日：2023-02-07

申请号：US16822389

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkweon Baek ,  Taeyoung Kim ,  Hakseon Kim ,  Kangoh Yun ,  Changhoon Jeon ,  Junhee Lim

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure disposed on a substrate. The gate structure has a first sidewall and a second sidewall facing the first sidewall. A first impurity region is disposed within an upper portion of the substrate. The first impurity region is spaced apart from the first sidewall. A third impurity region is within the upper portion of the substrate. The third impurity region is spaced apart from the second sidewall. A first trench is disposed within the substrate between the first sidewall and the first impurity region. The first trench is spaced apart from the first sidewall. A first barrier insulation pattern is disposed within the first trench.