公开(公告)号：US20240071771A1

公开(公告)日：2024-02-29

申请号：US18355520

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo KIM ,  Yonghan PARK ,  Jiho PARK ,  Geumjung SEONG ,  Seunguk HAN

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/3086

Abstract: A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.

公开(公告)号：US20130168774A1

公开(公告)日：2013-07-04

申请号：US13727995

申请日：2012-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namho JEON ,  Min-chul PARK ,  Seunguk HAN

IPC: H01L27/088

CPC classification number: H01L27/088 ,  G11C11/4085 ,  G11C11/4087 ,  H01L27/0207 ,  H01L27/10897

Abstract: A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离层限定的有源区，沿着第一方向在衬底上延伸并且彼此间隔开的栅电极，栅极突片沿与第一方向不同的第二方向延伸并连接相邻 栅极彼此间隔开，栅极突片彼此间隔开;以及第一接触插塞，其设置在由相邻的栅电极和相邻的栅极接线片限定的空间之下的有源区域上。 空间可以包括具有第一宽度的第一区域和具有小于第一宽度的第二宽度的第二区域，第一接触插塞可以设置在第二区域下方的有源区域上。