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公开(公告)号：US20160217085A1
公开(公告)日：2016-07-28
申请号：US15090842
申请日：2016-04-05
发明人： Kwon Taek KWON , Seok Yoon JUNG , Shi Hwa LEE
CPC分类号： G06F13/102 , G06F13/20 , G06F15/8023
摘要： A processor for processing stream data at a high speed is provided. The processor may include a functional unit to perform an operation on the stream data, an input interface module to perform relaying between the functional unit and an external data producer module that is used to input the stream data to the processor, and an output interface module to perform relaying between the functional unit and an external data consumer module that is used to receive an input of result data regarding a result of the operation performed by the functional unit.
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公开(公告)号：US20140029851A1
公开(公告)日：2014-01-30
申请号：US13872499
申请日：2013-04-29
发明人： Yong Min TAI , Young Su MOON , Jung Uk CHO , Joon Hyuk CHA , Shi Hwa LEE , Hyun Sang PARK
IPC分类号： G06K9/46
CPC分类号： G06K9/4642 , G06K9/00228 , G06K9/4647
摘要： An apparatus and method for calculating a cumulative histogram of an image are provided. A cumulative histogram calculation apparatus may include a cumulative value selecting unit to select cumulative data obtained by accumulating input data, based on a number of combinations of the input data, and a loading unit to load the selected cumulative value in a corresponding bin of a histogram.
摘要翻译： 提供了一种用于计算图像的累积直方图的装置和方法。 累积直方图计算装置可以包括累积值选择单元，用于基于输入数据的组合的数量和加载单元来选择通过累积输入数据而获得的累积数据，以将所选择的累积值加载到直方图的相应仓中 。
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公开(公告)号：US20140344602A1
公开(公告)日：2014-11-20
申请号：US14275311
申请日：2014-05-12
发明人： Min Young SON , Seung Won LEE , Shi Hwa LEE , Jae Don LEE , Chae Seok IM , Min Kyu JEONG
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3243 , G06F1/329 , G06F8/4432 , Y02B70/16 , Y02D10/152 , Y02D10/24 , Y02D10/41
摘要： A processing apparatus for managing power based on data is provided. The processing apparatus may obtain, in response to an access request from a processor for particular data stored in a memory, existing power information having a predefined correspondence to the particular data, and control a power mode of the processor based on the existing power information.
摘要翻译： 提供了一种用于基于数据管理电力的处理装置。 处理装置可以响应于处理器对存储在存储器中的特定数据的访问请求而获得具有与特定数据的预定对应关系的现有功率信息，并且基于现有功率信息来控制处理器的功率模式。
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4.发明申请公开(公告)号：US20140258690A1
公开(公告)日：2014-09-11
申请号：US14199154
申请日：2014-03-06
发明人： Kwon Taek KWON , Sang Oak WOO , Shi Hwa LEE , Seok Yoon JUNG
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/3832 , G06F9/3842 , G06F9/3859
摘要： An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.
摘要翻译： 一种用于非阻塞执行静态预定处理器的装置和方法，该装置包括处理器，用于使用传送的输入数据处理至少一个操作，以及用于将输入数据传送到处理器的输入缓冲器， 处理所述至少一个操作，其中所述处理器可以包括执行所述至少一个操作的至少一个功能单元（FU），并且所述至少一个FU可以使用常规等待时间操作和 不规则的延迟操作。
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公开(公告)号：US20130246797A1
公开(公告)日：2013-09-19
申请号：US13775999
申请日：2013-02-25
发明人： Min Kyu JEONG , Yong Sam SHIN , Seung Won LEE , Shi Hwa LEE
IPC分类号： H04L9/32
CPC分类号： H04L9/3255 , H04L9/3247
摘要： An apparatus for electronic signature verification, including a grouping unit to group, into at least one group, a plurality of kernels included in an application to which electronic signature verification is to be performed, and an electronic signature verification unit to perform electronic signature verification with respect to the at least one group.
摘要翻译： 一种用于电子签名验证的装置，包括分组单元，分组至少一组，包括在要执行电子签名验证的应用中的多个内核，以及电子签名验证单元，用于执行电子签名验证， 尊重至少一个组。
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公开(公告)号：US20140032976A1
公开(公告)日：2014-01-30
申请号：US13890675
申请日：2013-05-09
发明人： Young Sam SHIN , Seung Won LEE , Shi Hwa LEE , Min Young SON , Jae Don LEE
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F11/0721 , G06F11/0763
摘要： An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection apparatus may measure a deterministic progress index (DPI) and a program counter (PC) value when an instruction is executed, set, as a verification set, a DPI and a PC value measured when the instruction is executed without causing an error, set, as a measurement set, the DPI and the PC value measured when an instruction is executed, and detect a runtime error of the instruction by comparing the measurement set to the verification set.
摘要翻译： 提供了一种用于检测在计算机环境中执行应用程序时发生的错误的装置和方法。 错误检测装置可以在执行指令时设置指令执行确定性进度指标（DPI）和程序计数器（PC）值，作为验证集，执行指令时测量的DPI和PC值，而不引起错误 ，作为测量集，设置执行指令时测量的DPI和PC值，并通过将测量集与验证集进行比较来检测指令的运行时间错误。
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公开(公告)号：US20140015838A1
公开(公告)日：2014-01-16
申请号：US13940780
申请日：2013-07-12
发明人： Jeong Joon YOO , Seok Yoon JUNG , Seung Won LEE , Shi Hwa LEE
IPC分类号： G06T11/20
CPC分类号： G06T11/203 , G06T11/20 , G09G2360/122
摘要： An apparatus and method for tile binning with respect to a Bezier curve. The apparatus may include a curve identification unit to identify a Bezier curve included in input data, a bounding box generation unit to generate a plurality of bounding boxes corresponding to the Bezier curve, and a tile binning unit to perform tile binning with respect to the Bezier curve based on the plurality of bounding boxes.
摘要翻译： 一种用于相对于贝塞尔曲线的瓦片合并的装置和方法。 该装置可以包括用于识别包括在输入数据中的贝塞尔曲线的曲线识别单元，生成与贝塞尔曲线相对应的多个边界框的边界框生成单元，以及相对于贝塞尔曲线图进行瓦片合并的瓦片合并单元 基于多个边界框的曲线。
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公开(公告)号：US20170308410A1
公开(公告)日：2017-10-26
申请号：US15646747
申请日：2017-07-11
发明人： Min Young SON , Shi Hwa LEE , Seung Won LEE , Jeong Joon YOO , Jae Don LEE , Young Sam SHIN , Hee Jin AHN
CPC分类号： G06F9/5088 , G06F8/447 , G06F9/45558 , G06F11/3466 , G06F2009/4557
摘要： A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.
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公开(公告)号：US20140378838A1
公开(公告)日：2014-12-25
申请号：US14308920
申请日：2014-06-19
发明人： Chang Yong SON , Do Hyung KIM , Min Soo KIM , Kang Eun LEE , Shi Hwa LEE
IPC分类号： A61B8/00
CPC分类号： A61B8/4281 , A61B8/5207 , A61B8/54 , G01S7/52023 , G01S7/52079 , G10K11/341
摘要： An apparatus for beamforming including a multi-cluster architecture is disclosed, in which, a number of unit clusters including a reconfigurable processor and a co-processor may vary based on requirements.
摘要翻译： 公开了一种用于包括多集群架构的波束成形的装置，其中包括可重新配置的处理器和协处理器的多个单元群可以根据要求而变化。
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公开(公告)号：US20140297290A1
公开(公告)日：2014-10-02
申请号：US14157157
申请日：2014-01-16
发明人： Kang Eun Lee , Do Hyung KIM , Chang Yong SON , Shi Hwa LEE
IPC分类号： G10L19/002
CPC分类号： G10L19/173 , G10L19/035
摘要： An apparatus and method for decoding audio data. The apparatus for decoding the audio data may perform block data unpacking by preferring a channel order to a block order from a bitstream, and perform dithering through preferring a block order to a channel order. Complexity in decoding may be reduced through integrating bitstream searching and the bock data unpacking, and a dithering error may be prevented through processing the block data unpacking and the dithering separately.
摘要翻译： 一种用于对音频数据进行解码的装置和方法。 用于对音频数据进行解码的装置可以通过优选从比特流的频道顺序到块顺序来执行块数据解包，并且通过优选块顺序到频道顺序来执行抖动。 可以通过集成比特流搜索和块状数据解包来减少解码的复杂度，并且可以通过分别处理块数据解包和抖动来防止抖动错误。
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