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    VERTICAL NON-VOLATILE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
    1.
    发明公开
    VERTICAL NON-VOLATILE MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240206180A1

    公开(公告)日：2024-06-20

    申请号：US18341066

    申请日：2023-06-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsung Choi ,  Byongju Kim ,  Youjung Kim ,  Chaeho Kim ,  Changheon Cheon

    IPC: H01L29/792

    CPC classification number: H10B43/35 ,  H10B43/27

    Abstract: A vertical non-volatile memory device may include a mold structure including first and second insulation patterns and a first gate electrode, a semiconductor pattern extending through the mold structure in a first direction, a first charge insulation layer between the first insulation pattern and the semiconductor pattern, a second charge insulation layer spaced apart from the first charge insulation layer and between the second insulation pattern and the semiconductor pattern, a charge storage layer between the first and second charge insulation layers and between the first gate electrode and the semiconductor pattern, and a first blocking insulation layer between the first gate electrode and the charge storage layer, and a first length in the first direction of the first gate electrode is shorter than a second length in the first direction of a first surface of the charge storage layer which is in contact with the first blocking insulation layer.

    Methods of forming a semiconductor device
    3.
    发明授权
    Methods of forming a semiconductor device 有权
    形成半导体器件的方法

    公开(公告)号：US08980731B2

    公开(公告)日：2015-03-17

    申请号：US13724632

    申请日：2012-12-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

    IPC: H01L21/04 ,  H01L21/82 ,  H01L21/336 ,  H01L21/3205 ,  H01L29/76 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC classification number: H01L21/04 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

    Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC SYSTEM
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME, AND ELECTRONIC SYSTEM 有权

    公开(公告)号：US20250017009A1

    公开(公告)日：2025-01-09

    申请号：US18442229

    申请日：2024-02-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Siyeong Yang ,  Yuyeon Kim ,  Chaeho Kim

    IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B80/00

    Abstract: A semiconductor device includes a gate stacking structure, a channel structure, and a horizontal conductive layer. The gate stacking structure may include a plurality of gate electrodes and a plurality of insulation layers that are alternately stacked. The channel structure may be provided with an inner portion extending into the gate stacking structure and a protruded portion that protrudes from one surface of the gate stacking structure. The horizontal conductive layer may be connected to the protruded portion of the channel structure. In this case, the channel structure may include a semiconductor layer. The semiconductor layer may include a polycrystalline region in at least the protruded portion and including a polycrystalline semiconductor material and in a channel region positioned in the inner portion and having a crystal structure different from a crystal structure of the polycrystalline region.

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