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公开(公告)号:US20240206180A1
公开(公告)日:2024-06-20
申请号:US18341066
申请日:2023-06-26
发明人: Dongsung Choi , Byongju Kim , Youjung Kim , Chaeho Kim , Changheon Cheon
IPC分类号: H01L29/792
摘要: A vertical non-volatile memory device may include a mold structure including first and second insulation patterns and a first gate electrode, a semiconductor pattern extending through the mold structure in a first direction, a first charge insulation layer between the first insulation pattern and the semiconductor pattern, a second charge insulation layer spaced apart from the first charge insulation layer and between the second insulation pattern and the semiconductor pattern, a charge storage layer between the first and second charge insulation layers and between the first gate electrode and the semiconductor pattern, and a first blocking insulation layer between the first gate electrode and the charge storage layer, and a first length in the first direction of the first gate electrode is shorter than a second length in the first direction of a first surface of the charge storage layer which is in contact with the first blocking insulation layer.
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公开(公告)号:US10109747B2
公开(公告)日:2018-10-23
申请号:US14831449
申请日:2015-08-20
发明人: Byong-Hyun Jang , Juhyung Kim , Woonkyung Lee , Jaegoo Lee , Chaeho Kim , Junkyu Yang , Phil Ouk Nam , Jaeyoung Ahn , Kihyun Hwang
IPC分类号: H01L29/792 , H01L29/66 , H01L29/423 , H01L29/04 , H01L29/10 , H01L23/528 , H01L29/51 , H01L27/11582 , H01L27/1157
摘要: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.
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公开(公告)号:US08980731B2
公开(公告)日:2015-03-17
申请号:US13724632
申请日:2012-12-21
发明人: Jung Ho Kim , Sunghae Lee , Hanvit Yang , Dongwoo Kim , Chaeho Kim , Daehyun Jang , Ju-Eun Kim , Yong-Hoon Son , Sangryol Yang , Myoungbum Lee , Kihyun Hwang
IPC分类号: H01L21/04 , H01L21/82 , H01L21/336 , H01L21/3205 , H01L29/76 , H01L29/792 , H01L27/115 , H01L29/66
CPC分类号: H01L21/04 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.
摘要翻译: 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层,以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外,所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。
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公开(公告)号:US11532639B2
公开(公告)日:2022-12-20
申请号:US17036594
申请日:2020-09-29
发明人: Sangsoo Lee , Chaeho Kim , Woosung Lee , Phil Ouk Nam , Junggeun Jee
IPC分类号: H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L23/535 , H01L27/11565 , H01L27/11573 , H01L27/11529
摘要: Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.
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公开(公告)号:US09893082B2
公开(公告)日:2018-02-13
申请号:US15250091
申请日:2016-08-29
发明人: Chaeho Kim , Sangryol Yang , Woong Lee , SeungHyun Lim
IPC分类号: H01L27/115 , H01L29/423 , H01L27/11582 , H01L27/11573 , H01L29/51 , H01L27/11575 , H01L27/11565
CPC分类号: H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/42348 , H01L29/513
摘要: A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.
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公开(公告)号:US10208397B2
公开(公告)日:2019-02-19
申请号:US15204994
申请日:2016-07-07
发明人: Seung-Min Ryu , Sang Min Lee , Hee Jong Jeong , Chaeho Kim , Ji Su Son , Jaebong Lee , Juwan Lim , Jungwoo Choi
IPC分类号: C23C16/44 , C23C16/455 , C23C16/458 , C23C16/50 , C30B25/08 , C30B25/10 , C30B25/12 , C30B25/14 , C30B25/16 , C30B29/06 , C30B29/10 , C23C16/48 , C23C16/52
摘要: An apparatus is provided for depositing a thin film. The apparatus includes a chamber, a susceptor disposed in the chamber and supporting a substrate, a reflection housing disposed outside the chamber, a light source unit disposed in the reflection housing and irradiating light to the susceptor, and a light controlling unit blocking at least a portion of an irradiation path of the light to control an irradiation area of the light on the susceptor. At least a portion of the light controlling unit is disposed in the reflection housing.
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公开(公告)号:US09130054B2
公开(公告)日:2015-09-08
申请号:US13800872
申请日:2013-03-13
发明人: Byong-hyun Jang , Juhyung Kim , Woonkyung Lee , Jaegoo Lee , Chaeho Kim , Junkyu Yang , Phil Ouk Nam , Jaeyoung Ahn , Kihyun Hwang
IPC分类号: H01L21/20 , H01L29/792 , H01L29/66 , H01L27/115
CPC分类号: H01L29/792 , H01L23/528 , H01L27/1157 , H01L27/11582 , H01L29/045 , H01L29/1037 , H01L29/42364 , H01L29/511 , H01L29/66833 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.
摘要翻译: 一种半导体存储器件及其制造方法。 该器件包括垂直堆叠在衬底的顶表面上的多个栅极,该衬底的顶表面上形成有在该衬底中形成的外延层,垂直穿过该栅极的垂直沟道以与该外延层电连接;以及存储层,设置在该垂直沟道 和大门。 外延层具有位于最下面一个栅极的底表面和基板的顶表面之间的高度的顶表面。
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