公开(公告)号：US10164057B1

公开(公告)日：2018-12-25

申请号：US15878711

申请日：2018-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US20180315662A1

公开(公告)日：2018-11-01

申请号：US15854311

申请日：2017-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG YUB JEON ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66666

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US10312156B2

公开(公告)日：2019-06-04

申请号：US15838665

申请日：2017-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Yeon Jeong ,  Myung Gil Kang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.

公开(公告)号：US10892347B2

公开(公告)日：2021-01-12

申请号：US16197752

申请日：2018-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/739

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US10804160B2

公开(公告)日：2020-10-13

申请号：US16507529

申请日：2019-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US09786784B1

公开(公告)日：2017-10-10

申请号：US15271660

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Seung Song ,  Soo Yeon Jeong ,  Hyung Suk Lee

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A T-shaped fin structure extend vertically from an upper surface of a substrate. The T-shaped fin structure includes a lower part and an upper part. The lower part is in contact with the upper surface of the substrate. The upper part of the T-shaped fin structure is vertically stacked on the lower part of the T-shaped fin structure. A gate insulating layer surrounds the lower part. A work-function-control pattern surrounds the lower part. The gate insulating layer is interposed between the work-function-control pattern and the lower part of the T-shaped fin structure. A gate electrode is disposed on a sidewall of the work-function-control pattern.

公开(公告)号：US11462537B2

公开(公告)日：2022-10-04

申请号：US16919300

申请日：2020-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeong Han Gwon ,  Soo Yeon Jeong ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L27/092 ,  H01L23/535 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a first lower pattern and a second lower pattern on the substrate and arranged in a line in a first direction, a first active pattern stack disposed on and spaced apart from the first lower pattern, a second active pattern stack disposed on and spaced apart from the first lower pattern, a fin-cut gate structure disposed on the first lower pattern and overlapping a portion of the first lower pattern, a first gate structure surrounding the first active pattern stack and extending in a second direction crossing the first direction, a second gate structure surrounding the second active pattern stack and extending in the second direction, and a device isolation layer between the first gate structure and the second gate structure and separating the first lower pattern and the second lower pattern.

公开(公告)号：US20190333825A1

公开(公告)日：2019-10-31

申请号：US16507529

申请日：2019-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer, are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US10373878B2

公开(公告)日：2019-08-06

申请号：US15854311

申请日：2017-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Yub Jeon ,  Soo Yeon Jeong ,  Jae Kwang Choi

IPC: H01L21/8234 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device is provided. A first vertical structure and a second vertical structure are formed on a substrate. The second vertical structure is positioned right next to the first vertical structure. The second vertical structure is positioned right next to the first vertical structure. An insulating layer is formed on the substrate between the first and second vertical structures. A gate metal and a gate dielectric layer are formed on the first and second vertical structures. A portion of the gate metal, gate dielectric layer, and insulating layer is removed. A portion of the substrate is removed. The portion of the substrate is removed after the gate metal is formed on the first and second vertical structure.

公开(公告)号：US09870957B2

公开(公告)日：2018-01-16

申请号：US15290456

申请日：2016-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo Yeon Jeong ,  Myung Gil Kang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/417 ,  H01L29/49 ,  H01L23/535 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from an upper surface of the lower S/D. The fin structure includes a sidewall having an upper sidewall portion, a lower sidewall portion and a center sidewall portion positioned therebetween. An upper S/D is disposed on an upper surface of the fin structure. An upper spacer is disposed on the upper sidewall portion. A lower spacer is disposed on the lower sidewall portion. A stacked structure including a gate oxide layer and a first gate electrode is disposed on an upper surface of the lower spacer, the center sidewall portion and a lower surface of the upper spacer. A second gate electrode is disposed on the first gate electrode.