公开(公告)号：US20240341094A1

公开(公告)日：2024-10-10

申请号：US18522352

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoun Seo ,  Daeho Kim ,  Su Jong Kim ,  Sangho Rha ,  Byung-Sun Park ,  Mingyu Jeon

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/0651

Abstract: A semiconductor device may include a substrate including a cell array region and a connection region, a stack including electrodes, which are vertically stacked on the substrate, and which have a staircase structure in the connection region, channel regions provided on the cell array region that vertically extend through the stack, and a planarization insulating layer that covers the stack in the connection region. The planarization insulating layer may include a first insulating layer in contact with the stack and a second insulating layer that covers the first insulating layer. The first insulating layer may include high-density plasma (HDP) oxide, which is doped with first dopants, and the second insulating layer may include tetraethyl orthosilicate (TEOS) oxide, which is doped with second dopants.

公开(公告)号：US11581326B2

公开(公告)日：2023-02-14

申请号：US16913705

申请日：2020-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Jong Han ,  Jaekang Koh ,  Munjun Kim ,  Su Jong Kim ,  Seung-Heon Lee

IPC: H01L27/11573 ,  H01L23/528 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1158 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.