公开(公告)号：US20200266213A1

公开(公告)日：2020-08-20

申请号：US16870082

申请日：2020-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20190326321A1

公开(公告)日：2019-10-24

申请号：US16459337

申请日：2019-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil KIM ,  Seul Ye KIM ,  Hong Suk KIM ,  Jin Tae NOH ,  Ji Hoon CHOI ,  Jae Young AHN

IPC: H01L27/11582 ,  H01L27/108 ,  H01L23/532 ,  H01L27/11565 ,  H01L29/06 ,  H01L23/00 ,  H01L25/065

Abstract: A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

公开(公告)号：US20230328963A1

公开(公告)日：2023-10-12

申请号：US18062264

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Seo KIM ,  Sung Gil KIM ,  Ji Hun NOH

IPC: H10B12/00

CPC classification number: H01L27/10814

Abstract: A semiconductor memory device including a substrate including an active area defined by an element isolation layer, a bit line extending in a first direction on the substrate, a storage contact on each of both sides of the bit line and connected to the active area, a storage pad on the storage contact and connected to the storage contact and an information storage portion on the storage pad and connected to the storage pad, wherein the storage contact includes a lower storage contact and an upper storage contact on the lower storage contact, at least a portion of the lower storage contact is in the substrate, an entire upper surface of the lower storage contact is in contact with an entire lower surface of the upper storage contact, and each of the lower storage contact and the upper storage contact includes a semiconductor material may be provided.

公开(公告)号：US20220068968A1

公开(公告)日：2022-03-03

申请号：US17523014

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20230328967A1

公开(公告)日：2023-10-12

申请号：US18067390

申请日：2022-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hun NOH ,  Beom Seo KIM ,  Sung Gil KIM

IPC: H10B12/00

CPC classification number: H01L27/10888 ,  H01L27/10814 ,  H01L27/10823

Abstract: A semiconductor memory device may include a substrate including an active area defined by an element isolation layer on the substrate, a word line crossing the active area and extending in a first direction, a bit line crossing the active area on the substrate and extending in a second direction, and a bit line contact directly connected to the bit line and the active area. The bit line contact may be between the substrate and the bit line. The bit line contact may include a lower bit line contact directly connected to the active area and an upper bit line contact on and in contact with the lower bit line contact. A width of an upper surface of the lower bit line contact in the second direction may be greater than a width of a lower surface of the upper bit line contact in the second direction.

公开(公告)号：US20230180458A1

公开(公告)日：2023-06-08

申请号：US17933363

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BEOM SEO KIM ,  Bo Ram GU ,  Ja Min KOO ,  Sung Gil KIM ,  Jong Hyeok KIM

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063

Abstract: A semiconductor memory device includes a substrate including an active area defined by an element separation layer, the active area including a first portion and second portions defined on both sides of the first portion a bit line crossing the active area and extending in a first direction on the substrate, and a bit line contact disposed between the substrate and the bit line and directly connected to the first portion of the active area. The bit line contact includes an indent area recessed into the substrate and an upper area on the indent area, a width of the indent area decreases as a distance from the bit line increases, the indent area includes a slope forming a boundary with the substrate and having a straight line shape, and a starting point of the slope of the indent area is lower than an upper surface of the element separation layer.

公开(公告)号：US20190027495A1

公开(公告)日：2019-01-24

申请号：US16142637

申请日：2018-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.