公开(公告)号：US20220068968A1

公开(公告)日：2022-03-03

申请号：US17523014

申请日：2021-11-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11565

摘要： A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20190326321A1

公开(公告)日：2019-10-24

申请号：US16459337

申请日：2019-07-01

申请人： Samsung Electronics Co., Ltd.

发明人： Sung Gil KIM ,  Seul Ye KIM ,  Hong Suk KIM ,  Jin Tae NOH ,  Ji Hoon CHOI ,  Jae Young AHN

IPC分类号： H01L27/11582 ,  H01L27/108 ,  H01L23/532 ,  H01L27/11565 ,  H01L29/06 ,  H01L23/00 ,  H01L25/065

摘要： A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.

公开(公告)号：US20180331119A1

公开(公告)日：2018-11-15

申请号：US16027667

申请日：2018-07-05

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jung Ho KIM ,  BiO KIM ,  Hyung Joon KIM ,  Young Seon SON ,  Su Jin SHIN ,  Jae Young AHN ,  Ju Mi YUN ,  HanMei CHOI

IPC分类号： H01L27/11582 ,  H01L29/792 ,  H01L21/28 ,  H01L27/11568 ,  H01L27/11565

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/7926

摘要： A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

公开(公告)号：US20180315621A1

公开(公告)日：2018-11-01

申请号：US15791795

申请日：2017-10-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yong Seok CHO ,  Hyung Joon KIM ,  Jung Ho KIM ,  Joong Yun RA ,  Bi O KIM ,  Jae Young AHN ,  Ki Yong OH ,  Sung Hae LEE

IPC分类号： H01L21/56 ,  H01L21/8239 ,  H01L21/768 ,  H01L21/28 ,  H01L21/8234

CPC分类号： H01L21/565 ,  H01L21/28088 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/8239 ,  H01L27/10876 ,  H01L27/11582 ,  H01L29/40117

摘要： A method for fabricating a semiconductor device, the method including forming a mold structure on a substrate such that the mold structure includes alternately and repeatedly stacked interlayer insulating films and sacrificial films; forming a channel hole passing through the mold structure; forming a vertical channel structure within the channel hole; exposing a surface of the interlayer insulating films by removing the sacrificial films; forming an aluminum oxide film along a surface of the interlayer insulating films; forming a continuous film on the aluminum oxide film; and nitriding the continuous film to form a TiN film.

公开(公告)号：US20190027495A1

公开(公告)日：2019-01-24

申请号：US16142637

申请日：2018-09-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11565

摘要： A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20200266213A1

公开(公告)日：2020-08-20

申请号：US16870082

申请日：2020-05-08

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ji Hoon CHOI ,  Sung Gil KIM ,  Seulye KIM ,  Jung Ho KIM ,  Hong Suk KIM ,  Phil Ouk NAM ,  Jae Young AHN ,  Han Jin LIM

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11565

摘要： A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US20180366554A1

公开(公告)日：2018-12-20

申请号：US15871055

申请日：2018-01-14

申请人： Samsung Electronics Co., Ltd.

发明人： Eun Yeoung CHOI ,  Jun Kyu YANG ,  Young Jin NOH ,  Jae Young AHN ,  Jae Hyun YANG ,  Dong Chul YOO ,  Jae Ho CHOI

IPC分类号： H01L29/51 ,  H01L27/11582 ,  H01L27/11565

CPC分类号： H01L29/513 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.