Abstract:
A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.
Abstract:
A washing control method that is capable of controlling laundry to be effectively washed with bubbles depending upon load of a washing machine. The washing control method includes supplying wash water containing detergent into a space between a lower portion of a rotary drum and a lower inner surface of a water tub; heating the wash water containing detergent; generating and supplying bubbles into the rotary drum; and washing laundry with the supplied bubbles.
Abstract:
A washing control method that is capable of controlling laundry to be effectively washed with bubbles depending upon load of a washing machine. The washing control method includes supplying wash water containing detergent into a space between a lower portion of a rotary drum and a lower inner surface of a water tub; heating the wash water containing detergent; generating and supplying bubbles into the rotary drum; and washing laundry with the supplied bubbles.
Abstract:
An electronic device is provided. The electronic device includes a battery having a rated charging voltage, a rated charging current, and a design capacity, a charging circuit configured to supply power to the battery, and a processor electrically connected to the battery and the charging circuit. The processor is configured to control the charging circuit to charge the battery in different ways based on a plurality of ranges determined based on a full charge capacity (FCC) of the battery, and, when the FCC of the battery is included in a first range from the design capacity to a first capacity lower than the design capacity, control the charging circuit to charge the battery by setting a first voltage lower than the rated charging voltage and setting a first current lower than the rated charging current.
Abstract:
A memory device includes a memory cell array, a column decoder, and a row decoder. The memory cell array includes a plurality of antifuse memory cells arranged in rows and columns, each of the antifuse memory cells connected to one of a plurality of word lines, one of a plurality of high-voltage lines, and one of a plurality of bit lines. The column decoder is arranged at a first side of the memory cell array and configured to select one bit line among the bit lines. The row decoder is arranged parallel to the column decoder in a first direction, and configured to select one word line among the word lines.