公开(公告)号：US20240155844A1

公开(公告)日：2024-05-09

申请号：US18415460

申请日：2024-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung Hun Lee ,  Dong Ha Shin ,  Pan Suk Kwak ,  Dae Seok Byeon

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.

公开(公告)号：US11737271B2

公开(公告)日：2023-08-22

申请号：US16993570

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong Kwon ,  Chan Ho Kim ,  Kyung Hwa Yun ,  Dae Seok Byeon ,  Chi Weon Yoon

IPC: H10B43/27 ,  G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C5/14 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C5/145 ,  G11C16/08 ,  G11C16/24 ,  G11C16/32 ,  H10B43/35 ,  H10B43/40

Abstract: In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor memory device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

公开(公告)号：US11676836B2

公开(公告)日：2023-06-13

申请号：US17536551

申请日：2021-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ick Son ,  Dae Seok Byeon ,  Bong Soon Lim

IPC: H01L21/67 ,  G11C8/14 ,  H01L21/66 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C7/18 ,  H01L25/18

CPC classification number: H01L21/67288 ,  G11C7/18 ,  G11C8/14 ,  H01L22/34 ,  H01L24/05 ,  H01L24/20 ,  H01L25/18 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2924/1443

Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sensing line extending along an edge portion of the first semiconductor chip, an edge portion of the second semiconductor chip, or the edge portion of the first semiconductor chip and the edge portion of the second semiconductor chip; and a detecting circuit in the second semiconductor chip, the detecting circuit being configured to detect defects from the first semiconductor chip, the second semiconductor chip, or both the first semiconductor chip and the second semiconductor chip using the sensing line.

公开(公告)号：US10916314B2

公开(公告)日：2021-02-09

申请号：US16744763

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Jin Shin ,  Ji Su Kim ,  Dae Seok Byeon ,  Ji Sang Lee ,  Jun Jin Kong ,  Eun Chu Oh

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/10 ,  G11C5/14 ,  G11C16/24 ,  G11C16/08 ,  G11C16/32 ,  G11C11/56

Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

公开(公告)号：US10910080B2

公开(公告)日：2021-02-02

申请号：US16865675

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae Bang ,  Seung Hwan Song ,  Dae Seok Byeon ,  Il Han Park ,  Hyun Jun Yoon ,  Han Jun Lee ,  Na Young Choi

IPC: G11C27/00 ,  G11C11/56 ,  G06F11/10 ,  G11C16/28 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US10811107B2

公开(公告)日：2020-10-20

申请号：US16531926

申请日：2019-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Ho Na ,  Young Sun Min ,  Dae Seok Byeon

IPC: G11C16/30 ,  G11C5/14 ,  G11C16/04 ,  H03F3/45 ,  G11C16/08

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.

公开(公告)号：US20200273528A1

公开(公告)日：2020-08-27

申请号：US16531926

申请日：2019-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Ho NA ,  Young Sun Min ,  Dae Seok Byeon

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  H03F3/45

Abstract: Provided are a semiconductor memory device and a memory system including the same. The semiconductor memory device includes an external power supply voltage terminal configured to receive an external power supply voltage, an external ground voltage terminal configured to receive an external ground voltage, a ground voltage noise detector configured to detect a difference between the external ground voltage and an internal ground voltage of an internal ground voltage node and generate a ground voltage noise reference voltage, an internal power supply voltage reference voltage generator configured to generate an internal power supply voltage reference voltage based on the external power supply voltage and the ground voltage noise reference voltage, and an internal power supply voltage driver configured to generate an internal power supply voltage based on the internal power supply voltage reference voltage.

公开(公告)号：US10665312B2

公开(公告)日：2020-05-26

申请号：US16154111

申请日：2018-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bae Bang ,  Seung Hwan Song ,  Dae Seok Byeon ,  Il Han Park ,  Hyun Jun Yoon ,  Han Jun Lee ,  Na Young Choi

IPC: G11C27/00 ,  G11C11/56 ,  G06F11/10 ,  G11C16/28 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

Abstract: A nonvolatile memory device may include a page buffer including a plurality of latch sets that latch each page datum of selected memory cells among a plurality of memory cells according to each of read signal sets including at least one read signal, and a control logic configured to detect a degradation level of the memory cells and determine a read parameter applied to at least one of the read signal sets based on the detected degradation level.

公开(公告)号：US11756944B2

公开(公告)日：2023-09-12

申请号：US17023533

申请日：2020-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Bum Kim ,  Sung Hoon Kim ,  Dae Seok Byeon

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/544 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor wafer includes unit regions that are repeatedly arranged, and each unit region of the unit regions includes: at least one first chip region; and at least one second chip region spaced apart from the at least one first chip region by a scribe line, wherein a first area size of each of the at least one first chip region is different from a second area size of each of the at least one second chip region from a planar viewpoint.

公开(公告)号：US11716205B2

公开(公告)日：2023-08-01

申请号：US17161124

申请日：2021-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Ho Kim ,  Dae Seok Byeon

IPC: H04L9/32 ,  H04L9/08 ,  G11C16/04 ,  H04L9/14

CPC classification number: H04L9/3249 ,  G11C16/0483 ,  H04L9/0825 ,  H04L9/0861 ,  H04L9/14

Abstract: A memory device includes nonvolatile memory cells, and a secure module to process first data including information about the device stored in the cells to generate a first password key, process second data including information about the device stored in the cells to generate a second password key, generate a public key and a secret key by a public-key cryptography algorithm, using the first password key and the second password key, and provide the first password key, the second password key, the public key, and the secret key to the cells to store the first password key, the second password key, the public key, and the secret key, where the second data is different from the first data, a value of the first password key value and a value of the second password key are prime numbers, and the public key is provided to a host connected to the device.