公开(公告)号：US20200176464A1

公开(公告)日：2020-06-04

申请号：US16512513

申请日：2019-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hoon Jang ,  Woo Sung YANG ,  Joon Sung LIM ,  Sung Min HWANG

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

公开(公告)号：US20220028885A1

公开(公告)日：2022-01-27

申请号：US17203122

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Young KIM ,  Woo Sung YANG ,  Sung-Min HWANG ,  Suk Kang SUNG ,  Joon-Sung LIM

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

公开(公告)号：US20240215245A1

公开(公告)日：2024-06-27

申请号：US18595737

申请日：2024-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Young KIM ,  Woo Sung YANG ,  Sung-Min HWANG ,  Suk Kang SUNG ,  Joon-Sung LIM

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

公开(公告)号：US20240071907A1

公开(公告)日：2024-02-29

申请号：US18197768

申请日：2023-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah Reum LEE ,  Woo Sung YANG ,  Ji Mo GU ,  Jao Ho KIM ,  Suk Kang SUNG

IPC: H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L23/528 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes first and second substrates connected to each other. The second substrate includes a plate layer having first and second faces. Gate electrode layers are disposed on the first face of the plate layer. Channel structures extend through the gate electrode layers. Word-line cutting structures extend through the gate electrode layers and are spaced apart from each other. Via structures are disposed on the second face of the plate layer. Via connecting structures are disposed on the top face of the via structures. A width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures. A width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures.