公开(公告)号：US20220246200A1

公开(公告)日：2022-08-04

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu KIM ,  Namhyung KIM ,  Daejeong KIM ,  Dohan KIM ,  Chanik PARK ,  Deokho SEO ,  Wonjae SHIN ,  Changmin LEE ,  Ilguy JUNG ,  Insu CHOI

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row

公开(公告)号：US20240020234A1

公开(公告)日：2024-01-18

申请号：US18140410

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohwan OH ,  Wonjae SHIN ,  Eunbyeol KO

IPC: G06F12/0842

CPC classification number: G06F12/0842 ,  G06F2212/272

Abstract: A method of operating a storage module, the method including setting a characteristic value based on information received from a host, the information including information related to a size of write data in units of cache lines, and successively receiving the write data in units of the cache lines based on a single write command received from the host.

公开(公告)号：US20190303282A1

公开(公告)日：2019-10-03

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong KIM ,  Jiseok KANG ,  Tae-Kyeong KO ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Wonjae SHIN ,  Yongjun YU ,  Insu CHOI

IPC: G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G11C11/56

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.