公开(公告)号：US12232260B2

公开(公告)日：2025-02-18

申请号：US17939546

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjin Lee ,  Jonghoon Kim ,  Kyoungsun Kim ,  Sungjoo Park ,  Jinseong Yun ,  Young-Ho Lee ,  Jeonghyeon Cho ,  Heejin Cho

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/40

Abstract: An electronic device includes: a multilayered base substrate including a plurality of substrate bases stacked on each other; a first conductive via and a second conductive via penetrating the substrate bases and spaced from each other; a conductive line electrically connecting the first conductive via and the second conductive via to each other and disposed on at least one of the substrate bases of the plurality of substrate bases; and an open stub including a first end and a second end, wherein the first end is connected to a connector of the conductive line, and the second end is opened.

公开(公告)号：US11956890B2

公开(公告)日：2024-04-09

申请号：US17720364

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunho Lee ,  Yoojeong Kwon ,  Kyoungsun Kim ,  Dongyeop Kim ,  Sungjoo Park

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/11 ,  H05K1/18 ,  G11C11/401 ,  G11C16/04

CPC classification number: H05K1/0245 ,  H01P3/088 ,  H05K1/115 ,  H05K1/181 ,  G11C11/401 ,  G11C16/0483 ,  H05K2201/10159

Abstract: A circuit board includes a first insulating layer; a first wiring pattern and a second wiring pattern each formed to be side to side with each other on an upper surface of the first insulating layer; a second insulating layer formed on the upper surface of the first insulating layer to cover the first and second wiring patterns; a third wiring pattern formed on an upper surface of the second insulating layer to overlap the first wiring pattern in a vertical direction; a fourth wiring pattern formed on the upper surface of the second insulating layer to overlap the second wiring pattern in the vertical direction; a first via passing through the second insulating layer and connecting the first and fourth wiring patterns; and a second via passing through the second insulating layer and connecting the second and third wiring patterns.

公开(公告)号：US20200342917A1

公开(公告)日：2020-10-29

申请号：US16709984

申请日：2019-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyudong Lee ,  Young Yun ,  Sungjoo Park ,  Jinseong Yun

IPC: G11C5/14

Abstract: A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.

公开(公告)号：US20230035640A1

公开(公告)日：2023-02-02

申请号：US17938780

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyudong Lee ,  Young Yun ,  Sungjoo Park ,  Jinseong Yun

IPC: G11C5/14

Abstract: A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.