公开(公告)号：US09812220B2

公开(公告)日：2017-11-07

申请号：US15207557

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC: G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4076 ,  G11C11/4093 ,  G11C5/04

CPC classification number: G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US10978170B2

公开(公告)日：2021-04-13

申请号：US16124379

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-ho Lee ,  Sung-joo Park ,  Young Yun ,  Yong-jin Kim ,  Jae-jun Lee

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C11/409 ,  G11C7/10 ,  G01K7/01 ,  H05K1/11 ,  H05K1/18 ,  G11C5/04

Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation includes receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.

公开(公告)号：US20230035640A1

公开(公告)日：2023-02-02

申请号：US17938780

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyudong Lee ,  Young Yun ,  Sungjoo Park ,  Jinseong Yun

IPC: G11C5/14

Abstract: A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.

公开(公告)号：US20200342917A1

公开(公告)日：2020-10-29

申请号：US16709984

申请日：2019-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyudong Lee ,  Young Yun ,  Sungjoo Park ,  Jinseong Yun

IPC: G11C5/14

Abstract: A memory module includes a serial presence detector (SPD) configured to detect a module identification (ID) through at least one module position identification terminal, and generate at least one of the module ID and a register address corresponding to the module ID. A power management unit (PMU) is responsive to at least one of the module ID and the register address generated by the SPD. The PMU is configured to set an on-time point and/or an off-time point of an internal clock signal based on at least one of the module ID and the register address corresponding to the module ID, and further configured to generate at least one internal power supply voltage in response to the internal clock signal. A plurality of memory devices are also provided, which are configured to receive the at least one internal power supply voltage and perform an operation in response to command/address signals.

公开(公告)号：US09922724B2

公开(公告)日：2018-03-20

申请号：US15713936

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC: G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4093 ,  G11C11/4076 ,  G11C5/04

CPC classification number: G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US20170092379A1

公开(公告)日：2017-03-30

申请号：US15207557

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC: G11C29/34 ,  G06F12/1009 ,  G06F3/06 ,  G11C11/4093 ,  G11C11/4076

CPC classification number: G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US20190237152A1

公开(公告)日：2019-08-01

申请号：US16124379

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-ho Lee ,  Sung-joo Park ,  Young Yun ,  Yong-jin Kim ,  Jae-jun Lee

IPC: G11C29/38 ,  G11C29/36 ,  G11C11/409

CPC classification number: G11C29/38 ,  G01K7/01 ,  G11C11/409 ,  G11C29/36 ,  H05K1/117 ,  H05K1/181 ,  H05K2201/10151 ,  H05K2201/10159 ,  H05K2201/10522

Abstract: A memory device including: a loopback circuit for performing a loopback operation, wherein the loopback operation comprises receiving, via a loopback channel, test signals provided from a test device and feeding back the test signals to the test device via the loopback channel; and an information management circuit for outputting information of the memory device to the loopback channel.