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公开(公告)号：US10930675B2
公开(公告)日：2021-02-23
申请号：US16669639
申请日：2019-10-31
发明人： Jae-Woo Seo , Ki-Man Park , Ha-Young Kim , Junghwan Shin , Keunho Lee , Sungwe Cho
IPC分类号： H03K3/289 , H01L27/118 , H01L27/02 , H03K3/3562
摘要： Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.
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公开(公告)号：USRE49780E1
公开(公告)日：2024-01-02
申请号：US16916419
申请日：2020-06-30
发明人： Taejoong Song , Sanghoon Baek , Sungwe Cho , Jung-Ho Do , Giyoung Yang , Jinyoung Lim
IPC分类号： H01L27/02 , H01L27/118 , G06F30/394
CPC分类号： G06F30/394 , H01L27/0207 , H01L27/11807
摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
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公开(公告)号：US11756949B2
公开(公告)日：2023-09-12
申请号：US17246108
申请日：2021-04-30
发明人： Sungwe Cho , Subin Jin
IPC分类号： H01L27/02 , G06F30/392 , H01L23/528 , H01L27/092
CPC分类号： H01L27/0207 , G06F30/392 , H01L23/5286 , H01L27/0924
摘要： An integrated circuit includes at least one decoupling cell, wherein the at least one decoupling cell includes at least one P-type decoupling MOSFET and at least one N-type decoupling MOSFET, and a number of the at least one P-type decoupling MOSFET is different from a number of the at least one N-type decoupling MOSFET.
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公开(公告)号：US10720909B2
公开(公告)日：2020-07-21
申请号：US16522835
申请日：2019-07-26
发明人： Ha-Young Kim , Dalhee Lee , Hyoung-Suk Oh , Keunho Lee , Taejoong Song , Sungwe Cho
IPC分类号： H03K3/356 , H03K3/3562 , H03K23/00
摘要： A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
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公开(公告)号：US11989497B2
公开(公告)日：2024-05-21
申请号：US17517126
申请日：2021-11-02
发明人： Sungwe Cho
IPC分类号： G06F30/392 , G06F30/398 , H01L27/02 , G06F111/04
CPC分类号： G06F30/392 , G06F30/398 , H01L27/0207 , G06F2111/04
摘要： A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells.
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公开(公告)号：US20220229965A1
公开(公告)日：2022-07-21
申请号：US17517126
申请日：2021-11-02
发明人： Sungwe Cho
IPC分类号： G06F30/392 , G06F30/398 , H01L27/02
摘要： A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells.
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公开(公告)号：US11201172B2
公开(公告)日：2021-12-14
申请号：US17153939
申请日：2021-01-21
发明人： Jae-Woo Seo , Ki-Man Park , Ha-Young Kim , Junghwan Shin , Keunho Lee , Sungwe Cho
IPC分类号： H03K3/356 , H01L27/118 , H01L27/02 , H03K3/3562
摘要： Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.
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公开(公告)号：US10411677B2
公开(公告)日：2019-09-10
申请号：US15649776
申请日：2017-07-14
发明人： Ha-Young Kim , Dalhee Lee , Hyoung-Suk Oh , Keunho Lee , Taejoong Song , Sungwe Cho
IPC分类号： H03K3/356 , H03K23/00 , H03K3/3562
摘要： A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
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公开(公告)号：US10037401B2
公开(公告)日：2018-07-31
申请号：US15896415
申请日：2018-02-14
发明人： Taejoong Song , Sanghoon Baek , Sungwe Cho , Jung-Ho Do , Giyoung Yang , Jinyoung Lim
IPC分类号： G06F17/50 , H01L27/118 , H01L27/02
CPC分类号： G06F17/5077 , H01L27/0207 , H01L27/11807
摘要： A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
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