公开(公告)号：US10720909B2

公开(公告)日：2020-07-21

申请号：US16522835

申请日：2019-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Dalhee Lee ,  Hyoung-Suk Oh ,  Keunho Lee ,  Taejoong Song ,  Sungwe Cho

IPC: H03K3/356 ,  H03K3/3562 ,  H03K23/00

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

公开(公告)号：US10930675B2

公开(公告)日：2021-02-23

申请号：US16669639

申请日：2019-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Ki-Man Park ,  Ha-Young Kim ,  Junghwan Shin ,  Keunho Lee ,  Sungwe Cho

IPC: H03K3/289 ,  H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

公开(公告)号：US20220189945A1

公开(公告)日：2022-06-16

申请号：US17545009

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeha Lee ,  Jintae Kim ,  Keunho Lee ,  Dongyeon Heo

IPC: H01L27/02 ,  G06F30/392

Abstract: An integrated circuit includes: a first cell arranged in a first row extending in a first direction and performing a first function, a second cell arranged in the first row and performing a second function, a third cell arranged in a second row extending in the first direction and performing the first function, a fourth cell arranged in the second row and performing the second function, a first connection line connecting a first via in the first cell to a second via in the second cell, and a second connection line connecting a third via in the third cell to a fourth via in the fourth cell, wherein a length of the first connection line is different from a length of the second connection line.

公开(公告)号：US11201172B2

公开(公告)日：2021-12-14

申请号：US17153939

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Ki-Man Park ,  Ha-Young Kim ,  Junghwan Shin ,  Keunho Lee ,  Sungwe Cho

IPC: H03K3/356 ,  H01L27/118 ,  H01L27/02 ,  H03K3/3562

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

公开(公告)号：US10411677B2

公开(公告)日：2019-09-10

申请号：US15649776

申请日：2017-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-Young Kim ,  Dalhee Lee ,  Hyoung-Suk Oh ,  Keunho Lee ,  Taejoong Song ,  Sungwe Cho

IPC: H03K3/356 ,  H03K23/00 ,  H03K3/3562

Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.

公开(公告)号：US09634092B2

公开(公告)日：2017-04-25

申请号：US15046455

申请日：2016-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna Kumar Bhuwalka ,  Zhenhua Wu ,  Uihui Kwon ,  Keunho Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/0676 ,  H01L29/1037 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7782 ,  H01L29/785 ,  H01L29/78696

Abstract: Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.

公开(公告)号：US20160086841A1

公开(公告)日：2016-03-24

申请号：US14711394

申请日：2015-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHYUN SONG ,  Hyeon Kyun Noh ,  Taeyong Kwon ,  Sangsu Kim ,  Shigenobu Maeda ,  Krishna Bhuwalka ,  Uihui Kwon ,  Keunho Lee ,  Wonsok Lee

IPC: H01L21/762 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.

Abstract translation: 提供了一种用于形成半导体器件的图案的方法和使用其形成的半导体器件。 该方法包括在衬底上形成缓冲层，在缓冲层上形成沟道层，形成穿透沟道层的支撑图案，并通过图案化沟道层和缓冲层形成沟道鳍图案和缓冲图案。 沟道层包括晶格常数与缓冲层的晶格常数不同的材料，并且每个沟道鳍图案具有与支撑图案接触并且彼此相对的两个侧壁。