Method of fabricating three-dimensional semiconductor memory device

    公开(公告)号:US11805710B2

    公开(公告)日:2023-10-31

    申请号:US17395043

    申请日:2021-08-05

    CPC classification number: H10N70/063 H10B63/84 H10N70/068

    Abstract: A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.

    Methods of revising overlay correction data

    公开(公告)号:US09679821B2

    公开(公告)日:2017-06-13

    申请号:US15001729

    申请日:2016-01-20

    Abstract: Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

    Method of fabricating a semiconductor device with an overlay key pattern

    公开(公告)号:US10825777B2

    公开(公告)日:2020-11-03

    申请号:US16361546

    申请日:2019-03-22

    Abstract: A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region. The method includes forming a first layer on the substrate. The first layer has a first hole on the first region and a second hole on the second region. The method includes forming a second layer in the first hole and the second hole. The method includes forming a mask pattern on the second region of the substrate. The method includes polishing the second layer to form a pattern in the first hole and an overlay key pattern in the second hole. A top surface of the overlay key pattern is further from the substrate than a top surface of the pattern in the first hole.

    METHODS OF REVISING OVERLAY CORRECTION DATA
    6.
    发明申请
    METHODS OF REVISING OVERLAY CORRECTION DATA 有权
    修改覆盖数据的方法

    公开(公告)号:US20160351455A1

    公开(公告)日:2016-12-01

    申请号:US15001729

    申请日:2016-01-20

    Abstract: Provided are methods of generating and revising overlay correction data, a method of performing a photolithography process using the overlay correction data, and a method of performing a photolithography process while revising the overlay correction data. The method of revising the overlay correction data includes forming a plurality of overlay keys on a first set of wafers using first overlay correction data, measuring first overlay keys formed on first overlay coordinates in a first shot area of a first wafer among the first set of wafers, generating first overlay error data, and revising primarily the first overlay correction data using the first overlay error data, measuring second overlay keys formed on second overlay coordinates in a second shot area of a second wafer among the first set of wafers, generating second overlay error data, and revising secondarily the primarily revised first overlay correction data using the second overlay error data, and measuring third overlay keys formed on third overlay coordinates in a third shot area of a third wafer among the first set of wafers, generating third overlay error data, revising tertiarily the secondarily revised first overlay correction data, and generating second overlay correction data. The first overlay coordinates, the second overlay coordinates, and the third overlay coordinates are mutually exclusive.

    Abstract translation: 提供了生成和修改覆盖校正数据的方法,使用覆盖校正数据执行光刻处理的方法,以及在修改覆盖校正数据的同时执行光刻处理的方法。 修改覆盖校正数据的方法包括使用第一覆盖校正数据在第一组晶片上形成多个覆盖键,测量在第一组中的第一晶片的第一覆盖坐标中形成的第一覆盖坐标, 生成第一重叠错误数据,并且使用第一重叠错误数据主要修改第一重叠校正数据,测量形成在第一组晶片中的第二晶片的第二拍摄区域中的第二覆盖坐标上的第二重叠键,产生第二叠加错误数据 重叠错误数据,并且使用第二覆盖误差数据二次修改主要修改的第一覆盖校正数据,以及测量形成在第一晶片组中的第三晶片的第三拍摄区域中的第三覆盖坐标上的第三覆盖键,生成第三覆盖 错误数据,二次修改二次修改的第一重叠校正数据,并产生第二叠加校正 数据。 第一覆盖坐标,第二覆盖坐标和第三覆盖坐标是相互排斥的。

Patent Agency Ranking