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公开(公告)号：US09553101B2
公开(公告)日：2017-01-24
申请号：US14258772
申请日：2014-04-22
发明人： Taekyung Kim , Kwang Soo Seol , Hyunchul Back , Jin-Soo Lim , Seong Soon Cho
IPC分类号： H01L27/115 , H01L27/06 , H01L27/24 , H01L29/66 , H01L29/788 , H01L29/792 , H01L45/00
CPC分类号： H01L27/11578 , H01L27/0688 , H01L27/11519 , H01L27/11556 , H01L27/11582 , H01L27/11597 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/10 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： A semiconductor device may include gate structures spaced apart above a top surface of a substrate. The gate structures may include a horizontal electrode extending in a first direction parallel with the top surface of a substrate. An isolation insulating layer may be disposed between the gate structures. A plurality of cell pillars may penetrate the horizontal electrode and connect to the substrate. The plurality of cell pillars may include a minimum spacing defined by a shortest distance between any two of the plurality of cell pillars. The thickness of the horizontal electrode may be greater than the minimum spacing of the cell pillars.
摘要翻译： 半导体器件可以包括在衬底的顶表面之上间隔开的栅极结构。 栅极结构可以包括在与衬底的顶表面平行的第一方向上延伸的水平电极。 隔离绝缘层可以设置在栅极结构之间。 多个单元柱可以穿透水平电极并连接到基板。 多个单元柱可以包括由多个单元柱中的任何两个之间的最短距离限定的最小间隔。 水平电极的厚度可以大于电池柱的最小间距。
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公开(公告)号：US12029040B2
公开(公告)日：2024-07-02
申请号：US18083163
申请日：2022-12-16
发明人： Taekyung Kim , Kwang Soo Seol , Seong Soon Cho , Sunghoi Hur , Jintae Kang
IPC分类号： H01L29/792 , H01L27/115 , H01L29/423 , H01L29/66 , H10B41/10 , H10B43/27 , H10B43/35
CPC分类号： H10B43/35 , H01L29/4234 , H01L29/7926 , H10B41/10 , H10B43/27
摘要： A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
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公开(公告)号：US11545503B2
公开(公告)日：2023-01-03
申请号：US16747652
申请日：2020-01-21
发明人： Taekyung Kim , Kwang Soo Seol , Seong Soon Cho , Sunghoi Hur , Jintae Kang
IPC分类号： H01L27/11582 , H01L27/1157 , H01L29/423 , H01L27/11519 , H01L29/792
摘要： A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
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公开(公告)号：US10541248B2
公开(公告)日：2020-01-21
申请号：US16045997
申请日：2018-07-26
发明人： Taekyung Kim , Kwang Soo Seol , Seong Soon Cho , Sunghoi Hur , Jintae Kang
IPC分类号： H01L23/528 , H01L27/115 , H01L27/11556 , H01L27/11582 , H01L27/1157 , H01L29/423 , H01L27/11519 , H01L29/792
摘要： A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.
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