公开(公告)号：US20240324206A1

公开(公告)日：2024-09-26

申请号：US18581174

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungik YOO ,  Seungbeom KO ,  Taemok GWON ,  Changjin SON ,  Chadong YEO ,  Seulji LEE ,  Seungmin LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A nonvolatile memory device includes a substrate including a memory cell region and a connection region; a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked; a channel structure passing through the mold structure in the memory cell region; a first cell contact passing through the mold structure in the connection region, connected to a first gate electrode and electrically disconnected from a second gate electrode; a plurality of support structures surrounding the first cell contact planarly in the connection region and extending through the mold structure; and a dam structure located between the first cell contact and the second gate electrode in the connection region and apart from the first cell contact with an insulating ring therebetween.

公开(公告)号：US20210391289A1

公开(公告)日：2021-12-16

申请号：US17172276

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Taemok GWON ,  Seungmin LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/00

Abstract: A semiconductor device includes first gate electrodes, a first channel structure penetrating the first gate electrodes and including a first channel layer and a first channel filling insulating layer, second gate electrodes above the first gate electrodes, a second channel structure penetrating the second gate electrodes and including a second channel layer and a second channel filling insulating layer, and a central wiring layer between the first gate electrodes and the second gate electrodes and connected to the first channel layer and the second channel layer, wherein the first channel layer and the second channel layer are connected to each other in a region surrounded by the central wiring layer, and the first channel filling insulating layer and the second channel filling insulating layer are connected to each other in a region surrounded by the central wiring layer.

公开(公告)号：US20220216226A1

公开(公告)日：2022-07-07

申请号：US17497200

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Taemok GWON ,  Junhyoung KIM ,  Hyunjae KIM ,  Youngbum WOO ,  Jongin YUN

IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/06

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.