公开(公告)号：US20230217661A1

公开(公告)日：2023-07-06

申请号：US17961070

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbum WOO ,  Joonsung LIM ,  Junhyoung KIM ,  Seungmin LEE

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.

公开(公告)号：US20220216226A1

公开(公告)日：2022-07-07

申请号：US17497200

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Taemok GWON ,  Junhyoung KIM ,  Hyunjae KIM ,  Youngbum WOO ,  Jongin YUN

IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/06

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.